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| author | Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> | 2020-01-19 16:32:08 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-04-02 16:04:22 +0000 |
| commit | 737e56aa56e5dce6c682580f8e89b80a0119107f (patch) | |
| tree | 75f38d89e6225c4094a48dcfc3ce3a8fd5d3a66f /src/soc/amd/stoneyridge | |
| parent | 5646a648dfc7fcc53ff4dc86ddbc40620ee4a86c (diff) | |
| download | coreboot-737e56aa56e5dce6c682580f8e89b80a0119107f.tar.xz | |
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of
flash had already been defined differently in Family 17h. To begin
removing Family 15h dependencies from the common/psp, change the
definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and
applying the command into a single one.
BUG=b:130660285
TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/2020364
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Tested-by: Eric Peers <epeers@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index aa3c322813..f08c12f32f 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -160,7 +160,7 @@ static void earliest_ramstage(void *unused) if (!s3_resume) { post_code(0x46); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0a209b0260..efe75b72e3 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -61,7 +61,7 @@ static void load_smu_fw1(void) cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); } static void agesa_call(void) |