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authorFelix Held <felix-coreboot@felixheld.de>2020-08-26 20:09:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-31 06:39:56 +0000
commit0d707303ee1d82a8a79b55c37f3d4d7944586820 (patch)
treeab9a4f1faf712bb4f72b396fa599ef7815ff7210 /src/soc/amd
parent0900bd09273017cf3ec2aabb218a8e87931b3393 (diff)
downloadcoreboot-0d707303ee1d82a8a79b55c37f3d4d7944586820.tar.xz
soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge. BUG=b:149970243 BRANCH=zork Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index e4ae8dca7e..033bcbfdbe 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -161,8 +161,6 @@
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
#define MISC_CLK_CNTL1 0x40
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
-#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
-#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
#define MISC_I2C0_PAD_CTRL 0xd8
#define MISC_I2C1_PAD_CTRL 0xdc
#define MISC_I2C2_PAD_CTRL 0xe0