diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-15 21:11:39 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-29 20:28:56 +0000 |
| commit | 27d02d8286aff64115ae593a189c38fdaf3ce769 (patch) | |
| tree | 53b2eccef24a14c530b5af9d75488a1ff9147342 /src/soc/amd | |
| parent | ab89edbccf6e614213bbd88f5dbd5c8bf9a5d4c6 (diff) | |
| download | coreboot-27d02d8286aff64115ae593a189c38fdaf3ce769.tar.xz | |
src/soc: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 2 |
3 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 25a564b457..512b0b8c04 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,7 +18,7 @@ #include <amdblocks/agesawrapper.h> #include <soc/pci_devs.h> -#include <stdint.h> +#include <types.h> /* Extra, Special Purpose Registers in the PSP PCI Config Space */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 563dae09e1..60a6ea22bb 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -18,6 +18,7 @@ #define __PI_STONEYRIDGE_NORTHBRIDGE_H__ #include <device/device.h> +#include <types.h> /* D0F0 - Root Complex */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index bf8787c1fc..84db3dd76c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -14,7 +14,6 @@ */ #include <console/console.h> - #include <device/mmio.h> #include <bootstate.h> #include <cpu/x86/smm.h> @@ -36,6 +35,7 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/nvs.h> +#include <types.h> /* * Table of devices that need their AOAC registers enabled and waited |