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authorRaul E Rangel <rrangel@chromium.org>2018-06-12 10:53:55 -0600
committerMartin Roth <martinroth@google.com>2018-06-12 18:04:52 +0000
commit873b4e70bc4c829307864f6819490840e07b6660 (patch)
treebd035c7d512015bdb0895ec57a45c1f8a40b7f28 /src/soc/amd
parentf1eff68ef5cb0df52450ce78bf203c9cd51a7888 (diff)
downloadcoreboot-873b4e70bc4c829307864f6819490840e07b6660.tar.xz
stoneyridge: Move agesa out of bootblock
This is Garrett's patch with a bit of cleanup. BUG=b:65442212 TEST=Was able to boot, suspend and resume on grunt. Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/bootblock/bootblock.c57
-rw-r--r--src/soc/amd/stoneyridge/romstage.c44
2 files changed, 44 insertions, 57 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 9cfbae374d..56f6437fb6 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -52,27 +52,6 @@ static void amd_initmmio(void)
set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
}
-/*
- * To move AGESA calls to romstage, just move agesa_call() and bsp_agesa_call()
- * to romstage.c. Also move the call to bsp_agesa_call() to the marked location
- * in romstage.c.
- */
-static void agesa_call(void)
-{
- post_code(0x37);
- do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");
-
- post_code(0x38);
- /* APs will not exit amdinitearly */
- do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");
-}
-
-static void bsp_agesa_call(void)
-{
- set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
- agesa_call();
-}
-
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
amd_initmmio();
@@ -97,37 +76,6 @@ void bootblock_soc_early_init(void)
post_code(0x90);
}
-/*
- * This step is in bootblock because the SMU FW1 must be loaded prior to
- * issuing any reset to the system. Set up just enough to get the command
- * to the PSP. A side effect of placing this step here is we will always
- * load a RO version of FW1 and never a RW version.
- *
- * todo: If AMD develops a more robust methodology, move this function to
- * romstage.
- */
-static void load_smu_fw1(void)
-{
- u32 base, limit, cmd;
-
- /* Open a posted hole from 0x80000000 : 0xfed00000-1 */
- base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
- limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
-
- /* Preload a value into "BAR3" and enable it */
- pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
- pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
-
- /* Enable memory access and master */
- cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
- cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
-
- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
-}
-
void bootblock_soc_init(void)
{
if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
@@ -137,11 +85,6 @@ void bootblock_soc_init(void)
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
- if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
- load_smu_fw1();
-
- bsp_agesa_call();
-
/* Initialize any early i2c buses. */
i2c_soc_early_init();
}
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index a742cd062d..78472d332a 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -41,6 +41,44 @@ void __weak mainboard_romstage_entry(int s3_resume)
/* By default, don't do anything */
}
+static void load_smu_fw1(void)
+{
+ u32 base, limit, cmd;
+
+ /* Open a posted hole from 0x80000000 : 0xfed00000-1 */
+ base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
+ limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
+
+ /* Preload a value into "BAR3" and enable it */
+ pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
+ pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
+
+ /* Enable memory access and master */
+ cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
+
+ psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
+}
+
+static void agesa_call(void)
+{
+ post_code(0x37);
+ do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");
+
+ post_code(0x38);
+ /* APs will not exit amdinitearly */
+ do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");
+}
+
+static void bsp_agesa_call(void)
+{
+ set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
+ agesa_call();
+}
+
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
@@ -61,6 +99,12 @@ asmlinkage void car_stage_entry(void)
console_init();
+ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
+ load_smu_fw1();
+
+
+ bsp_agesa_call();
+
mainboard_romstage_entry(s3_resume);
if (!s3_resume) {