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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-23 14:41:32 +0100
committerMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-25 15:19:52 +0000
commitb84c6167505ca76239b8bd59f4ebb3c115111de5 (patch)
tree381fb0347ea062f854cf0116b8b37879f8ed7b32 /src/soc/amd
parent612a8676779f873f2f7a3c8011ad0eac61ca38f9 (diff)
downloadcoreboot-b84c6167505ca76239b8bd59f4ebb3c115111de5.tar.xz
amd/common/acpi: move thermal zone to common location
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/common/acpi/thermal_zone.asl92
1 files changed, 92 insertions, 0 deletions
diff --git a/src/soc/amd/common/acpi/thermal_zone.asl b/src/soc/amd/common/acpi/thermal_zone.asl
new file mode 100644
index 0000000000..e6ab43235b
--- /dev/null
+++ b/src/soc/amd/common/acpi/thermal_zone.asl
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard DSDT inside the PCI device
+ * "Northbridge Miscellaneous Control (Northbridge function 3)" and it
+ * will expose the temperature sensor of the processor as a thermal
+ * zone.
+ *
+ * Families 10 through 14 and some family 15 CPUs are supported.
+ *
+ * If, for example, the NB Misc. Control device is on 0:18.3, include
+ * the following:
+ *
+ * Scope (\_SB.PCI0) {
+ * Device (K10M) {
+ * Name (_ADR, 0x00180003)
+ * #include <soc/amd/common/acpi/thermal_zone.asl>
+ * }
+ * }
+ *
+ * Do not include this if the board is affected by erratum 319 as the
+ * thermal sensor of Socket F/AM2+ processors may be unreliable.
+ * (Erratum 319 affects AM2+ boards, AM3 and later should be fine)
+ */
+
+#ifndef K10TEMP_HOT_OFFSET
+# define K10TEMP_HOT_OFFSET 50
+#endif
+
+#define K10TEMP_KELVIN_OFFSET 2732
+#define K10TEMP_TLIMIT_OFFSET 520
+
+OperationRegion (TCFG, PCI_Config, 0x64, 0x4)
+Field (TCFG, ByteAcc, NoLock, Preserve) {
+ HTCE, 1, /* Hardware thermal control enable */
+ , 15,
+ TLMT, 7, /* (LimitTmp - 52) / 0.5 */
+ , 9,
+}
+
+OperationRegion (TCTL, PCI_Config, 0xa4, 0x4)
+Field (TCTL, ByteAcc, NoLock, Preserve) {
+ , 21,
+ TNOW, 11, /* CurTmp / 0.125 */
+}
+
+ThermalZone (TZ00) {
+ Name (_STR, Unicode ("AMD CPU Core Thermal Sensor"))
+
+ Method (_STA) {
+ If (LEqual (HTCE, One)) {
+ Return (0x0F)
+ }
+ Return (Zero)
+ }
+
+ Method (_TMP) { /* Current temp in tenths degree Kelvin. */
+ Multiply (TNOW, 10, Local0)
+ ShiftRight (Local0, 3, Local0)
+ Return (Add (Local0, K10TEMP_KELVIN_OFFSET))
+ }
+
+ /*
+ * TLMT indicates threshold where HTC become active. That is the processor will limit
+ * P-State and power consumption in order to cool down.
+ */
+ Method (_PSV) { /* Passive temp in tenths degree Kelvin. */
+ Multiply (TLMT, 10, Local0)
+ ShiftRight (Local0, 1, Local0)
+ Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0)
+ Return (Add (Local0, K10TEMP_KELVIN_OFFSET))
+ }
+
+ Method (_HOT) { /* Hot temp in tenths degree Kelvin. */
+ Return (Add (_PSV, K10TEMP_HOT_OFFSET))
+ }
+
+ Method (_CRT) { /* Critical temp in tenths degree Kelvin. */
+ Return (Add (_HOT, K10TEMP_HOT_OFFSET))
+ }
+}