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authorFelix Held <felix-coreboot@felixheld.de>2021-02-09 23:43:17 +0100
committerMartin Roth <martinroth@google.com>2021-02-11 00:49:23 +0000
commitee2a3658727578721808620c526efa757f91aab0 (patch)
treeaa9b119098c95af2d738dbe90ad18fca231ce41c /src/soc/amd
parenta8d4a718e3a95dde5146e67790e15ca3f3b71cf7 (diff)
downloadcoreboot-ee2a3658727578721808620c526efa757f91aab0.tar.xz
soc/amd/cezanne: add empty SMM-handler
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/Kconfig14
-rw-r--r--src/soc/amd/cezanne/Makefile.inc3
-rw-r--r--src/soc/amd/cezanne/smihandler.c7
3 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 10c085e018..4949286c7c 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -17,6 +17,7 @@ config SOC_SPECIFIC_OPTIONS
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
select HAVE_CF9_RESET
+ select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select IOAPIC
select PLATFORM_USES_FSP2_0
@@ -154,6 +155,19 @@ config CONSOLE_UART_BASE_ADDRESS
default 0xfedc9000 if UART_FOR_CONSOLE = 0
default 0xfedca000 if UART_FOR_CONSOLE = 1
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
+ default 0x0
+
+config SMM_RESERVED_SIZE
+ hex
+ default 0x180000
+
+config SMM_MODULE_STACK_SIZE
+ hex
+ default 0x800
+
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index ce9f66ccc2..3501282b86 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/smm
# Beware that all-y also adds the compilation unit to verstage on PSP
all-y += config.c
@@ -34,6 +35,8 @@ ramstage-y += reset.c
ramstage-y += root_complex.c
ramstage-y += uart.c
+smm-y += smihandler.c
+
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c
new file mode 100644
index 0000000000..2d9e487984
--- /dev/null
+++ b/src/soc/amd/cezanne/smihandler.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+
+void southbridge_smi_handler(void)
+{
+}