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authorMarc Jones <marcj303@gmail.com>2017-11-22 22:16:31 -0700
committerMartin Roth <martinroth@google.com>2017-12-06 16:23:44 +0000
commitfb4c7d250fb8940377551d224f2473aae0565290 (patch)
tree650be5b2bf3c8e0b426169954a6400c16491d866 /src/soc/amd
parent7654f86f3ab5ad87b7a224b075842a35b8b8748b (diff)
downloadcoreboot-fb4c7d250fb8940377551d224f2473aae0565290.tar.xz
soc/amd/stoneyridge: Add USB OC support
Add USB overcurrent support. Adds a weak call for mainboards that don't suport USB OC. BUG=b:69229635 Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h31
-rw-r--r--src/soc/amd/stoneyridge/usb.c34
2 files changed, 64 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index f840fd9296..3b9ea80934 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -268,6 +268,28 @@
#define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD BIT(1)
+#define XHCI_PM_INDIRECT_INDEX 0x48
+#define XHCI_PM_INDIRECT_DATA 0x4C
+#define XHCI_OVER_CURRENT_CONTROL 0x30
+
+#define EHCI_OVER_CURRENT_CONTROL 0x70
+
+#define USB_OC0 0
+#define USB_OC1 1
+#define USB_OC2 2
+#define USB_OC3 3
+#define USB_OC4 4
+#define USB_OC5 5
+#define USB_OC6 6
+#define USB_OC7 7
+#define USB_OC_DISABLE 0xf
+#define USB_OC_DISABLE_ALL 0xffff
+
+#define OC_PORT0_SHIFT 0
+#define OC_PORT1_SHIFT 4
+#define OC_PORT2_SHIFT 8
+#define OC_PORT3_SHIFT 12
+
static inline int sb_sata_enable(void)
{
/* True if IDE or AHCI. */
@@ -322,4 +344,13 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
void bootblock_fch_early_init(void);
+/*
+ * Call the mainboard to get the USB Over Current Map. The mainboard
+ * returns the map and 0 on Success or -1 on error or no map. There is
+ * a default weak function in usb.c if the mainboard doesn't have any
+ * over current support.
+ */
+int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map);
+int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map);
+
#endif /* __STONEYRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c
index 82984b9b82..0665976c89 100644
--- a/src/soc/amd/stoneyridge/usb.c
+++ b/src/soc/amd/stoneyridge/usb.c
@@ -20,8 +20,40 @@
#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <soc/pci_devs.h>
#include <soc/southbridge.h>
+
+static void set_usb_over_current(struct device *dev)
+{
+ uint16_t map = USB_OC_DISABLE_ALL;
+
+ if (dev->path.pci.devfn == XHCI_DEVFN) {
+ if (mainboard_get_xhci_oc_map(&map) == 0) {
+ xhci_pm_write32(XHCI_PM_INDIRECT_INDEX,
+ XHCI_OVER_CURRENT_CONTROL);
+ xhci_pm_write16(XHCI_PM_INDIRECT_DATA, map);
+ }
+ }
+
+ if (dev->path.pci.devfn == EHCI1_DEVFN) {
+ if (mainboard_get_ehci_oc_map(&map) == 0)
+ pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map);
+ }
+}
+
+int __attribute__((weak)) mainboard_get_xhci_oc_map(uint16_t *map)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+int __attribute__((weak)) mainboard_get_ehci_oc_map(uint16_t *map)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
static struct pci_operations lops_pci = {
.set_subsystem = pci_dev_set_subsystem,
};
@@ -30,7 +62,7 @@ static struct device_operations usb_ops = {
.read_resources = pci_ehci_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = NULL,
+ .init = set_usb_over_current,
.scan_bus = NULL,
.ops_pci = &lops_pci,
};