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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-09-04 16:13:08 -0600
committerMartin Roth <martinroth@google.com>2017-09-13 18:57:42 +0000
commit06766c1efaf7e9f502dc0705f31af0f234824cb7 (patch)
treeba63bc6603c6bdf735e4bccddf18f21f8fcc4749 /src/soc/amd
parent0801b335dd11f7827b6c0164f06d75e7a94fff1e (diff)
downloadcoreboot-06766c1efaf7e9f502dc0705f31af0f234824cb7.tar.xz
amd/stoneyridge: Remove PSP BAR init from cpu init
Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The BAR is configured in romstage by AmdInitPost(). Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/model_15_init.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index a46f322d14..631e89cb98 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -30,23 +30,6 @@
#include <cpu/amd/amdfam15.h>
#include <arch/acpi.h>
-#include <amdlib.h>
-#include <PspBaseLib.h>
-
-void PSPProgBar3Msr(void *Buffer);
-
-void PSPProgBar3Msr(void *Buffer)
-{
- u32 Bar3Addr;
- u64 Tmp64;
- /* Get Bar3 Addr */
- Bar3Addr = PspLibPciReadPspConfig(0x20);
- Tmp64 = Bar3Addr;
- printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
- LibAmdMsrWrite(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL);
- LibAmdMsrRead(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL);
-}
-
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
@@ -106,7 +89,6 @@ static void model_15_init(device_t dev)
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
- PSPProgBar3Msr(NULL);
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);