summaryrefslogtreecommitdiff
path: root/src/soc/amd
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-04-18 10:11:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-04-20 13:03:54 +0000
commite56189cfd1d90a2ca13650a9d21ff82cb79ccda8 (patch)
tree0da4c1fec6bdb725e4065d4d687364ae5c63104d /src/soc/amd
parent6fcb9b00c8b7f820bb5ef81a83a24cd656654272 (diff)
downloadcoreboot-e56189cfd1d90a2ca13650a9d21ff82cb79ccda8.tar.xz
pci: Move inline PCI functions to pci_ops.h
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/cpu.c1
-rw-r--r--src/soc/amd/stoneyridge/nb_util.c1
-rw-r--r--src/soc/amd/stoneyridge/reset.c1
-rw-r--r--src/soc/amd/stoneyridge/tsc_freq.c1
4 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 15dd38147c..2c415a3e25 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -21,6 +21,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam15.h>
#include <device/device.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
diff --git a/src/soc/amd/stoneyridge/nb_util.c b/src/soc/amd/stoneyridge/nb_util.c
index 4d3e53faf3..d5de067814 100644
--- a/src/soc/amd/stoneyridge/nb_util.c
+++ b/src/soc/amd/stoneyridge/nb_util.c
@@ -15,6 +15,7 @@
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
+#include <device/pci_ops.h>
uint32_t nb_ioapic_read(unsigned int index)
{
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index 886f33cdcc..a133a88b92 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -18,6 +18,7 @@
#include <reset.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
+#include <device/pci_ops.h>
#include <soc/southbridge.h>
/* Clear bits 5, 9 & 10, used to signal the reset type */
diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c
index 1f48306afe..8c18884001 100644
--- a/src/soc/amd/stoneyridge/tsc_freq.c
+++ b/src/soc/amd/stoneyridge/tsc_freq.c
@@ -21,6 +21,7 @@
#include <cpu/amd/amdfam15.h>
#include <console/console.h>
#include <soc/pci_devs.h>
+#include <device/pci_ops.h>
unsigned long tsc_freq_mhz(void)
{