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authorRizwan Qureshi <rizwan.qureshi@intel.com>2017-09-06 19:08:23 +0530
committerFurquan Shaikh <furquan@google.com>2017-09-15 18:20:42 +0000
commitea4649f65fece2e14a3f2b0d1b4f5835a76a1141 (patch)
tree5dc385e517c6832be5b5986bde4434300ca4d44c /src/soc/amd
parent6a051f2b49d5d4b9605f4a4a2dfe46cd770704b3 (diff)
downloadcoreboot-ea4649f65fece2e14a3f2b0d1b4f5835a76a1141.tar.xz
mb/google/poppy: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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