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authorFurquan Shaikh <furquan@google.com>2020-05-04 20:59:23 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-11 23:27:25 +0000
commitefe27cf3f978e7510b272a28b59779bc387c8106 (patch)
tree4aee70ba783d2339d06cff92211225c872f087bc /src/soc/amd
parent235a75128ab7642247bf0895a15c698c63eb13ba (diff)
downloadcoreboot-efe27cf3f978e7510b272a28b59779bc387c8106.tar.xz
soc/amd/common/block/lpc: Add config options for eSPI
eSPI on Picasso is configured using the LPC bridge configuration registers. This change enables config options to allow SoC to select if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to select if it wants to use eSPI instead of LPC for talking to legacy devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI). BUG=b:154445472 Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41069 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/common/block/lpc/Kconfig15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index 3cfbfe5dcd..1ec8dd4668 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -9,3 +9,18 @@ config PROVIDES_ROM_SHARING
default n
help
Select this option if the LPC bridge supports ROM sharing.
+
+config SOC_AMD_COMMON_BLOCK_HAS_ESPI
+ bool
+ default n
+ help
+ Select this option if platform supports eSPI using D14F3 configuration
+ registers.
+
+config SOC_AMD_COMMON_BLOCK_USE_ESPI
+ bool
+ depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
+ default n
+ help
+ Select this option if mainboard uses eSPI instead of LPC (if supported
+ by platform).