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| author | Duncan Laurie <dlaurie@google.com> | 2020-10-27 10:29:16 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-10-30 18:34:30 +0000 |
| commit | 2e9315c4c666f7c49a90298723ec043f79371602 (patch) | |
| tree | 233056ebbf1a77adc23ea3a97edd08f847abc84a /src/soc/amd | |
| parent | 0f5a17e98092dd6f340582ede5d481e53f90a06c (diff) | |
| download | coreboot-2e9315c4c666f7c49a90298723ec043f79371602.tar.xz | |
soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases
Enable the USB4 XHCI driver and remove the ACPI name entry from the
SOC level function.
Define aliases for the USB2/3 ports on north and south XHCI devices in
chipset.cb so they can be referenced in the mainboard devicetree.
BUG=b:151731851
TEST=define usb ports by reference in volteer devicetree and ensure
they get properties added in SSDT for both north and south XHCI device.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions