soc/amd/picasso: Add support for em100

This change enables support for em100 for Picasso platform. Since
em100 requires lower SPI speed, this change configures speed in all
modes as 16MHz.

BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that em100 works fine on trembyle.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 16 insertions, 1 deletions

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index fa053f98cc..5996cc632e 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_DESIGNWARE
 	select GENERIC_GPIO_LIB
 	select IOAPIC
+	select HAVE_EM100_SUPPORT
 	select HAVE_USBDEBUG_OPTIONS
 	select TSC_MONOTONIC_TIMER
 	select SOC_AMD_COMMON_BLOCK_SPI
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 4f25802141..d37f143313 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -236,7 +236,7 @@ void sb_read_mode(u32 mode)
 	write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode));
 }
 
-static void sb_spi_config_modes(void)
+static void sb_spi_config_mb_modes(void)
 {
 	const struct soc_amd_picasso_config *cfg = config_of_soc();
 
@@ -245,6 +245,20 @@ static void sb_spi_config_modes(void)
 		      cfg->spi_tpm_speed);
 }
 
+static void sb_spi_config_em100_modes(void)
+{
+	sb_read_mode(SPI_READ_MODE_NORMAL33M);
+	sb_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M);
+}
+
+static void sb_spi_config_modes(void)
+{
+	if (CONFIG(EM100))
+		sb_spi_config_em100_modes();
+	else
+		sb_spi_config_mb_modes();
+}
+
 static void sb_spi_init(void)
 {
 	lpc_enable_spi_prefetch();