soc/amd/stoneyridge/: Get rid of device_t

Use of device_t has been abandoned in ramstage.

Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

8 files changed, 39 insertions, 39 deletions

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 02ee6fa02f..735990f093 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -233,11 +233,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 }
 
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
 {
 	int cores, cpu, plen = 6;
 	u32 pcontrol_blk = ACPI_GPE0_BLK;
-	device_t cdb_dev;
+	struct device *cdb_dev;
 
 	/* Stoney Ridge is single node, just report # of cores */
 	cdb_dev = dev_find_slot(0, NB_DEVFN);
@@ -258,7 +258,7 @@ void generate_cpu_entries(device_t device)
 	}
 }
 
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
 		unsigned long current,
 		struct acpi_rsdp *rsdp)
 {
@@ -286,7 +286,7 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
 	gnvs->pcnt = dev_count_cpu();
 }
 
-void southbridge_inject_dsdt(device_t device)
+void southbridge_inject_dsdt(struct device *device)
 {
 	struct global_nvs_t *gnvs;
 
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 46dcfa80dd..3b73a054b8 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -107,7 +107,7 @@ struct device_operations pci_domain_ops = {
 	.acpi_name	  = soc_acpi_name,
 };
 
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 2c415a3e25..4dd371cdd3 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -55,7 +55,7 @@ static void pre_mp_init(void)
 
 static int get_cpu_count(void)
 {
-	device_t nb = dev_find_slot(0, HT_DEVFN);
+	struct device *nb = dev_find_slot(0, HT_DEVFN);
 	return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1;
 }
 
@@ -115,7 +115,7 @@ void stoney_init_cpus(struct device *dev)
 	mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
 }
 
-static void model_15_init(device_t dev)
+static void model_15_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Model 15 Init.\n");
 
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index 69ab599509..3212ec7cf7 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -30,10 +30,10 @@
 	#define FADT_PM_PROFILE PM_UNSPECIFIED
 #endif
 
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
 		unsigned long current, struct acpi_rsdp *rsdp);
 
-void southbridge_inject_dsdt(device_t device);
+void southbridge_inject_dsdt(struct device *device);
 
 const char *soc_acpi_name(const struct device *dev);
 
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 365a9f5eef..666be10e1e 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -107,9 +107,9 @@ void smm_region_info(void **start, size_t *size);
  * 0 on success, < 0 on failure.
  */
 int smm_subregion(int sub, void **start, size_t *size);
-void domain_enable_resources(device_t dev);
-void domain_read_resources(device_t dev);
-void domain_set_resources(device_t dev);
+void domain_enable_resources(struct device *dev);
+void domain_read_resources(struct device *dev);
+void domain_set_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
 void setup_uma_memory(void);
 uint32_t nb_ioapic_read(unsigned int index);
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index eb512817b6..4bf5a4f1b4 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -34,11 +34,11 @@
 #include <soc/southbridge.h>
 #include <soc/nvs.h>
 
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
 {
 	u8 byte;
 	u32 dword;
-	device_t sm_dev;
+	struct device *sm_dev;
 
 	/*
 	 * Enable the LPC Controller
@@ -108,7 +108,7 @@ static void lpc_init(device_t dev)
 	pm_write8(PM_SERIRQ_CONF, byte);
 }
 
-static void lpc_read_resources(device_t dev)
+static void lpc_read_resources(struct device *dev)
 {
 	struct resource *res;
 	global_nvs_t *gnvs;
@@ -165,7 +165,7 @@ static void lpc_set_resources(struct device *dev)
 	pci_dev_set_resources(dev);
 }
 
-static void set_child_resource(device_t child,
+static void set_child_resource(struct device *child,
 				u32 *reg,
 				u32 *reg_x)
 {
@@ -299,7 +299,7 @@ static void set_child_resource(device_t child,
  * @param dev the device whose children's resources are to be enabled
  *
  */
-static void lpc_enable_childrens_resources(device_t dev)
+static void lpc_enable_childrens_resources(struct device *dev)
 {
 	struct bus *link;
 	u32 reg, reg_x;
@@ -308,7 +308,7 @@ static void lpc_enable_childrens_resources(device_t dev)
 	reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 
 	for (link = dev->link_list; link; link = link->next) {
-		device_t child;
+		struct device *child;
 		for (child = link->children; child;
 		     child = child->sibling) {
 			if (child->enabled
@@ -323,7 +323,7 @@ static void lpc_enable_childrens_resources(device_t dev)
 	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x);
 }
 
-static void lpc_enable_resources(device_t dev)
+static void lpc_enable_resources(struct device *dev)
 {
 	pci_dev_enable_resources(dev);
 	lpc_enable_childrens_resources(dev);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 2cefb9161f..6af1351294 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -41,11 +41,11 @@
 #include <stdlib.h>
 #include <string.h>
 
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
 			u32 io_min, u32 io_max)
 {
 	u32 tempreg;
-	device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
+	struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
 
 	/* io range allocation.  Limit */
 	tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)
@@ -59,7 +59,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
 						u32 mmio_min, u32 mmio_max)
 {
 	u32 tempreg;
-	device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
+	struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
 
 	/* io range allocation.  Limit */
 	tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
@@ -68,7 +68,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
 		pci_write_config32(addr_map, reg, tempreg);
 }
 
-static void read_resources(device_t dev)
+static void read_resources(struct device *dev)
 {
 	struct resource *res;
 
@@ -86,7 +86,7 @@ static void read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
+static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
 {
 	resource_t rbase, rend;
 	unsigned int reg, link_num;
@@ -135,7 +135,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
  * but it is too difficult to deal with the resource allocation magic.
  */
 
-static void create_vga_resource(device_t dev)
+static void create_vga_resource(struct device *dev)
 {
 	struct bus *link;
 
@@ -154,7 +154,7 @@ static void create_vga_resource(device_t dev)
 	pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1);
 }
 
-static void set_resources(device_t dev)
+static void set_resources(struct device *dev)
 {
 	struct bus *bus;
 	struct resource *res;
@@ -197,7 +197,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static void northbridge_fill_ssdt_generator(device_t device)
+static void northbridge_fill_ssdt_generator(struct device *device)
 {
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";
@@ -218,7 +218,7 @@ static void northbridge_fill_ssdt_generator(device_t device)
 	acpigen_pop_len();
 }
 
-static unsigned long agesa_write_acpi_tables(device_t device,
+static unsigned long agesa_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     acpi_rsdp_t *rsdp)
 {
@@ -355,7 +355,7 @@ void amd_initcpuio(void)
 
 void fam15_finalize(void *chip_info)
 {
-	device_t dev;
+	struct device *dev;
 	u32 value;
 	dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */
 	pci_write_config32(dev, 0xf8, 0);
@@ -368,10 +368,10 @@ void fam15_finalize(void *chip_info)
 	pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value);
 }
 
-void domain_read_resources(device_t dev)
+void domain_read_resources(struct device *dev)
 {
 	unsigned int reg;
-	device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
+	struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
 
 	/* Find the already assigned resource pairs */
 	for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {
@@ -381,7 +381,7 @@ void domain_read_resources(device_t dev)
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
 			unsigned int nodeid, reg_link;
-			device_t reg_dev = dev_find_slot(0, HT_DEVFN);
+			struct device *reg_dev = dev_find_slot(0, HT_DEVFN);
 			if (reg < 0xc0) /* mmio */
 				nodeid = (limit & 0xf) + (base & 0x30);
 			else /* io */
@@ -405,14 +405,14 @@ void domain_read_resources(device_t dev)
 	pci_domain_read_resources(dev);
 }
 
-void domain_enable_resources(device_t dev)
+void domain_enable_resources(struct device *dev)
 {
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!romstage_handoff_is_resume())
 		do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid");
 }
 
-void domain_set_resources(device_t dev)
+void domain_set_resources(struct device *dev)
 {
 	uint64_t uma_base = get_uma_base();
 	uint32_t uma_size = get_uma_size();
diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c
index d4f428f343..278f8a8001 100644
--- a/src/soc/amd/stoneyridge/sm.c
+++ b/src/soc/amd/stoneyridge/sm.c
@@ -32,12 +32,12 @@
 * The southbridge enables SATA by default in SMBUS Control.
 */
 
-static void sm_init(device_t dev)
+static void sm_init(struct device *dev)
 {
 	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 }
 
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device *dev)
 {
 	u8 device;
 	struct resource *res;
@@ -51,7 +51,7 @@ static int lsmbus_recv_byte(device_t dev)
 	return do_smbus_recv_byte(res->base, device);
 }
 
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device *dev, u8 val)
 {
 	u8 device;
 	struct resource *res;
@@ -65,7 +65,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
 	return do_smbus_send_byte(res->base, device, val);
 }
 
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
 {
 	u8 device;
 	struct resource *res;
@@ -79,7 +79,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
 	return do_smbus_read_byte(res->base, device, address);
 }
 
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
 {
 	u8 device;
 	struct resource *res;