diff options
author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-05-16 12:09:37 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-06-12 21:15:16 +0000 |
commit | 9b05af367fde33fc620c4cd759c2b09cdc036cc9 (patch) | |
tree | 61fce7ebb6e70b88d978ee112e8575d70557eb3d /src/soc/amd | |
parent | 29cc33181a18e76d033a4f8dc5d3bbd982ce4b9b (diff) | |
download | coreboot-9b05af367fde33fc620c4cd759c2b09cdc036cc9.tar.xz |
soc/amd/stoneyridge/acpi: Create a GPIO library
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r-- | src/soc/amd/stoneyridge/acpi/gpio_lib.asl | 132 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/acpi/soc.asl | 3 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 1 |
3 files changed, 136 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl new file mode 100644 index 0000000000..fbd6525f53 --- /dev/null +++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +/* Get pin control MMIO address */ +Method (GPAD, 0x1) +{ + /* Arg0 - GPIO pin number */ + Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_BASE)) +} + +/* Read pin control dword */ +Method (GPRD, 0x1, Serialized) +{ + /* Arg0 - GPIO pin control MMIO address */ + Store (Arg0, Local0) + OperationRegion (GPDW, SystemMemory, Local0, 4) + Field (GPDW, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) +} + +/* Write pin control dword */ +Method (GPWR, 0x2, Serialized) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + Store (Arg0, Local0) + OperationRegion (GPDW, SystemMemory, Local0, 4) + Field (GPDW, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) +} + +Method (GPGB, 0x2) +{ + /* + * Returns the desired byte + * Arg0 - GPIO pin control MMIO address + * Arg1 - Desired byte (0 through 3) + */ + Store (Multiply(Arg1, 8), Local2) + Return (And(ShiftRight(GPRD(Arg0), Local2), 0x000000FF)) +} + +Method (GPSB, 0x3) +{ + /* + * Reads dword, replace byte, write back dword + * Arg0 - GPIO pin control MMIO address + * Arg1 - Desired byte (0 through 3) + * Arg2 - Value + */ + Store (Multiply(Arg1, 8), Local2) + And(ShiftRight(GPRD(Arg0), Local2), 0xFFFFFF00, Local3) + ShiftLeft (Or(And(Arg2, 0x000000FF),Local3), Local2, Local4) + GPWR (Arg0, Local4) +} + +/* Read pin control byte 0 */ +Method (GPR0, 0x1) +{ + /* Arg0 - GPIO pin control MMIO address */ + Return (GPGB(Arg0, 0)) +} + +/* Read pin control byte 1 */ +Method (GPR1, 0x1) +{ + /* Arg0 - GPIO pin control MMIO address */ + Return (GPGB(Arg0, 1)) +} + +/* Read pin control byte 2 */ +Method (GPR2, 0x1) +{ + /* Arg0 - GPIO pin control MMIO address */ + Return (GPGB(Arg0, 2)) +} + +/* Read pin control byte 3 */ +Method (GPR3, 0x1) +{ + Return (GPGB(Arg0, 3)) +} + +/* Write pin control byte 0 */ +Method (GPW0, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 0, Arg1) +} + +/* Write pin control byte 1 */ +Method (GPW1, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 1, Arg1) +} + +/* Write pin control byte 2 */ +Method (GPW2, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 2, Arg1) +} + +/* Write pin control byte 3 */ +Method (GPW3, 0x2) +{ + /* Arg0 - GPIO pin control MMIO address */ + /* Arg1 - Value for control register */ + GPSB (Arg0, 3, Arg1) +} diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index d7772948ef..6fd838a56d 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -26,3 +26,6 @@ Device(PCI0) { /* Describe the devices in the Southbridge */ #include "sb_fch.asl" + +/* Add GPIO library */ +#include <gpio_lib.asl> diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 01171c3cf8..341d97d687 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -39,6 +39,7 @@ #define BIOSRAM_MMIO_BASE 0xfed80500 #define IOMUX_MMIO_BASE 0xfed80d00 #define MISC_MMIO_BASE 0xfed80e00 +#define GPIO_CONTROL_BASE 0xfed81500 #define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 #define AOAC_MMIO_BASE 0xfed81e00 |