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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-25 16:06:12 -0600
committerMartin Roth <martinroth@google.com>2019-08-09 20:20:31 +0000
commitc17cc63e481af7f981abbb9e2383b8447a2224d3 (patch)
tree5a498a95fcc6e57039bdd28444b785d6a66f5770 /src/soc/amd
parent48c5d29cdeaa0cafccf511d7699f2eef1209122a (diff)
downloadcoreboot-c17cc63e481af7f981abbb9e2383b8447a2224d3.tar.xz
src/amd/picasso: Update reset code
Remove the scratch register indicators. Per AMD, AGESA no longer uses these. Use a new IO register to determine whether a warm reset should occur. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I0ff7935004b3d1ac5204d3ef575cfa98116a57fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/33989 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/include/soc/iomap.h1
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h3
-rw-r--r--src/soc/amd/picasso/reset.c23
3 files changed, 8 insertions, 19 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 1d89fd7ec0..2870103e93 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -69,6 +69,7 @@
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */
+#define NCP_ERR 0xf0
#define SMB_BASE_ADDR 0xb00
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 6fc37f009a..36880a14a3 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -279,6 +279,9 @@
#define RST_CMD BIT(2)
#define SYS_RST BIT(1)
+/* IO 0xf0 NCP Error */
+#define NCP_WARM_BOOT BIT(7) /* Write-once */
+
struct picasso_aoac {
int enable;
int status;
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c
index ec5ee910d9..98410387fb 100644
--- a/src/soc/amd/picasso/reset.c
+++ b/src/soc/amd/picasso/reset.c
@@ -25,32 +25,18 @@
void set_warm_reset_flag(void)
{
- u32 htic;
- htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
- htic |= HTIC_COLD_RST_DET;
- pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
-}
+ uint8_t ncp = inw(NCP_ERR);
-int is_warm_reset(void)
-{
- u32 htic;
- htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
- return !!(htic & HTIC_COLD_RST_DET);
+ outb(NCP_ERR, ncp | NCP_WARM_BOOT);
}
-/* Clear bits 5, 9 & 10, used to signal the reset type */
-static void clear_bios_reset(void)
+int is_warm_reset(void)
{
- u32 htic;
- htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
- htic &= ~HTIC_BIOSR_DETECT;
- pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
+ return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
}
void do_cold_reset(void)
{
- clear_bios_reset();
-
/* De-assert and then assert all PwrGood signals on CF9 reset. */
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
TOGGLE_ALL_PWR_GOOD);
@@ -60,7 +46,6 @@ void do_cold_reset(void)
void do_warm_reset(void)
{
set_warm_reset_flag();
- clear_bios_reset();
/* Assert reset signals only. */
outb(RST_CMD | SYS_RST, SYS_RESET);