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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-21 18:33:55 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-23 16:14:07 +0000 |
| commit | eb8e8df92a9805adfab8b411c2848cd64b220a63 (patch) | |
| tree | bae62fb4818572a08eb1cb6cf47ae91349ec5aa7 /src/soc/amd | |
| parent | 85e981c8c945a7d438e6b30f13036199799529d6 (diff) | |
| download | coreboot-eb8e8df92a9805adfab8b411c2848cd64b220a63.tar.xz | |
soc/amd/picasso/romstage: Set HDA disable UPD if controller disabled
FSP has recently added support for a UPD switch to disable the non-GPU
HD Audio controller. This change adds the coreboot side of the feature.
To avoid having two HD Audio enable options, the value of the
hd_audio_enable UPD is determined by the enable state of the non-GPU HD
Audio controller in the platform devicetree.
BUG=b:158535201,b:162302028
BRANCH=zork
TEST=With the corresponding FSP change applied the non-GPU HD Audio
device is hidden when switched off in devicetree and remains present and
functional when switched on in devicetree.
Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 342fd467ec..0accc49cfa 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -9,11 +9,13 @@ #include <console/uart.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <device/device.h> #include <program_loading.h> #include <elog.h> #include <soc/acpi.h> #include <soc/memmap.h> #include <soc/mrc_cache.h> +#include <soc/pci_devs.h> #include <types.h> #include "chip.h" #include <fsp/api.h> @@ -38,6 +40,30 @@ static void add_chipset_state_cbmem(int unused) ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem); +static const struct device_path hda_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = HD_AUDIO_DEVFN + }, +}; + +static bool devtree_hda_dev_enabled(void) +{ + const struct device *hda_dev; + + hda_dev = find_dev_nested_path(pci_root_bus(), hda_path, ARRAY_SIZE(hda_path)); + + if (!hda_dev) + return false; + + return hda_dev->enabled; +} + + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -88,6 +114,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; + mcfg->hd_audio_enable = devtree_hda_dev_enabled(); } asmlinkage void car_stage_entry(void) |