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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-09-04 11:32:25 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-10-20 16:28:46 +0000 |
| commit | f6dbf4a46a44e3cc63fa734d9a77e3bc6e622aa8 (patch) | |
| tree | 5027712b4f263dc67c7ecb2463819b90734d0c4b /src/soc/amd | |
| parent | e0fd9a60e7a869eed8bf368afe1e1ab6e6da7a6c (diff) | |
| download | coreboot-f6dbf4a46a44e3cc63fa734d9a77e3bc6e622aa8.tar.xz | |
soc/amd/common/lpc: Add SuperIO decode function
The LPC-ISA bridge supports two ranges for SuperIO control registers.
Add a generic function to allow a mainboard to enable the appropriate
range. Provide #define values that are more descriptive than the
register's field names.
Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/lpc.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc_util.c | 12 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 11880eb3e6..2874c18879 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -75,6 +75,8 @@ #define LPC_WIDEIO0_ENABLE BIT(2) #define DECODE_ALTERNATE_SIO_ENABLE BIT(1) #define DECODE_SIO_ENABLE BIT(0) +#define LPC_SELECT_SIO_4E4F 1 +#define LPC_SELECT_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 /* Assuming word access to higher word (register 0x4a) */ @@ -151,6 +153,8 @@ void soc_late_lpc_bridge_enable(void); void lpc_enable_port80(void); void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); +/* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */ +void lpc_enable_sio_decode(const bool addr); uintptr_t lpc_spibase(void); void lpc_tpm_decode(void); void lpc_tpm_decode_spi(void); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 1d46acbf5c..cdf36b2988 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -165,6 +165,18 @@ void lpc_enable_pci_port80(void) pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } +void lpc_enable_sio_decode(const bool addr) +{ + uint32_t decodes; + uint32_t enable; + + decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + enable = addr == LPC_SELECT_SIO_2E2F ? + DECODE_SIO_ENABLE : DECODE_ALTERNATE_SIO_ENABLE; + decodes |= enable; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes); +} + void lpc_enable_decode(uint32_t decodes) { pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); |