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authorSubrata Banik <subrata.banik@intel.com>2019-09-10 15:51:17 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-09-12 04:28:20 +0000
commit3eff037f8cbe99f72626c0f25c0989ea638599ef (patch)
treed4db81b1d76e96e38e6862389e8d183319a8ca9d /src/soc/amd
parentb3426c03b4cf84af871c6d4c32afed2086f3fd1a (diff)
downloadcoreboot-3eff037f8cbe99f72626c0f25c0989ea638599ef.tar.xz
soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to postcar_enable_tseg_cache(). BUG=b:140008206 Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/romstage.c13
-rw-r--r--src/soc/amd/stoneyridge/romstage.c13
2 files changed, 4 insertions, 22 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 4f18b42276..9882d9115e 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -44,8 +44,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
console_init();
@@ -87,15 +85,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 0d65ef6c82..4032d3f8b8 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -85,8 +85,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@@ -172,15 +170,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);