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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-07-16 12:56:03 -0600
committerMartin Roth <martinroth@google.com>2019-07-21 17:30:24 +0000
commit498de91e459bc5122fb72d2a486e1d74d17eaac5 (patch)
tree62ebd7be641a6efa1adf29dc47058107c6b9fd30 /src/soc/amd
parent917cc5cf2529f1ce387354941fb0a664919e8a91 (diff)
downloadcoreboot-498de91e459bc5122fb72d2a486e1d74d17eaac5.tar.xz
soc/amd/picasso: Enable stage cache only with ACPI resume
Make the option match the change in I7c3b3ec. "stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME" Change-Id: I7fa13428ec0119b61f429116a52986067e833bdf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index d654e9494e..d6445c7cb2 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -52,7 +52,7 @@ config CPU_SPECIFIC_OPTIONS
select C_ENVIRONMENT_BOOTBLOCK
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select HAVE_SMI_HANDLER