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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-09 11:46:32 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 16:52:48 +0000 |
| commit | 5d0893adced0423241dc016392ca9d4ce1340b2e (patch) | |
| tree | a20a207773a617fdfb4d2548d7d24f05e3a2410e /src/soc/amd | |
| parent | 83ca56acdfc7a98945f673c7739764ef25b967f2 (diff) | |
| download | coreboot-5d0893adced0423241dc016392ca9d4ce1340b2e.tar.xz | |
console, PCI: Remove EARLY_PCI_BRIDGE support in verstage
The purpose of pci_early_bridge_init() is to temporarily configure
PCIe rootport (or PCI bridge) on bus 0 to configure PCI device BARs
on the secondary bus. Currently used and tested only with UART_OXPCIE.
Since those BARs do not reset on stage changes, it is not necessary
to redo those steps for verstage or postcar. Note that the option
does not really work with many of the later platforms where PCIe
pins/links/lanes are configured late in FSP-M or similar blob.
Change-Id: I148f44c76c61edcfd8ab1c8c531cd2e6ca343130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions