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authorRaul E Rangel <rrangel@chromium.org>2020-05-19 16:13:06 -0600
committerFelix Held <felix-coreboot@felixheld.de>2020-05-21 22:28:26 +0000
commit6de79b9a1dedfb36e30a932f300de4ad8a5d27b4 (patch)
treea0b90d56326c4583ecf6e8388a690f39ce9f1351 /src/soc/amd
parent5df9a04640cf6ab97fab06ac2822c9a2640325b2 (diff)
downloadcoreboot-6de79b9a1dedfb36e30a932f300de4ad8a5d27b4.tar.xz
soc/amd/picasso/chip.c: Generate ACPI nodes for PCI Bridge A and B
This node is required so we can add child ACPI nodes. BUG=b:147042464 TEST=Boot trembyle and confirm Bus A has a firmware node $ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path \_SB_.PCI0.PBRA Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/chip.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 26dcbfb9df..f5936646d2 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -112,18 +112,35 @@ struct device_operations pci_domain_ops = {
.acpi_name = soc_acpi_name,
};
+static struct device_operations pci_ops_ops_bus_ab = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .acpi_fill_ssdt = acpi_device_write_pci_dev,
+};
+
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN)
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
- else if (dev->path.type == DEVICE_PATH_PCI)
+ } else if (dev->path.type == DEVICE_PATH_PCI) {
+ if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
+ switch (dev->path.pci.devfn) {
+ case PCIE_GPP_A_DEVFN:
+ case PCIE_GPP_B_DEVFN:
+ dev->ops = &pci_ops_ops_bus_ab;
+ }
+ }
sb_enable(dev);
- else if (dev->path.type == DEVICE_PATH_MMIO)
+ } else if (dev->path.type == DEVICE_PATH_MMIO) {
if (i2c_acpi_name(dev) != NULL)
dev->ops = &picasso_i2c_mmio_ops;
+ }
}
static void soc_init(void *chip_info)