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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2019-02-12 19:17:02 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-15 16:24:42 +0000 |
| commit | c93d4abb9986d561aa87fe5ac4643a0071c73f18 (patch) | |
| tree | ef3c2a49bcd504af4c07b8051950d86cac617eee /src/soc/amd | |
| parent | 8ca2af1c0d3a529bc7a9e6bd8bae16f9b941d42d (diff) | |
| download | coreboot-c93d4abb9986d561aa87fe5ac4643a0071c73f18.tar.xz | |
soc/amd/stoneyridge: Expand 48MHz for both osc out signals
There are typically two configurable oscillator outputs available on APUs
or FCHs. Convert the enable function to work with either one.
BUG=b:none.
TEST=Build and boot grunt.
Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 18 |
2 files changed, 15 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3ae6b4aa07..705fe7a533 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -186,6 +186,7 @@ #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ +#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ /* XHCI_PM Registers: 0xfed81c00 */ #define XHCI_PM_INDIRECT_INDEX 0x48 @@ -477,7 +478,7 @@ struct soc_power_reg { void enable_aoac_devices(void); void sb_enable_rom(void); void configure_stoneyridge_i2c(void); -void sb_clk_output_48Mhz(void); +void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c8d66ac3f2..dfbd160821 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -389,20 +389,28 @@ static void sb_enable_legacy_io(void) pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); } -void sb_clk_output_48Mhz(void) +void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE + MISC_CLK_CNTL1); /* - * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so - * 48Mhz will be on ball AP13 (FT3b package) + * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) + * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. */ ctrl = read32(misc_clk_cntl_1_ptr); - /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + switch (osc) { + case 1: + ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + break; + case 2: + ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; + break; + default: + return; /* do nothing if invalid */ + } write32(misc_clk_cntl_1_ptr, ctrl); } |