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authorFurquan Shaikh <furquan@google.com>2020-05-13 12:14:11 -0700
committerAaron Durbin <adurbin@chromium.org>2020-05-14 21:25:50 +0000
commitfc752b69183e0c2b37fa50f03d89aeb59c876c4f (patch)
tree31577a1e166e10947b28e4b9e770bd1e343db1b9 /src/soc/amd
parentffa5e8ddcfb099eff56eb8e6cd70ca4bd0b2545d (diff)
downloadcoreboot-fc752b69183e0c2b37fa50f03d89aeb59c876c4f.tar.xz
soc/amd/stoneyridge: add resources during read_resources()
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I532f508936d5ec154cbcb3538949316ae4851105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/chip.c4
-rw-r--r--src/soc/amd/stoneyridge/include/soc/northbridge.h2
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c6
3 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index f3c330c8a3..41fcafbab9 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -96,8 +96,8 @@ const char *soc_acpi_name(const struct device *dev)
};
struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = domain_set_resources,
+ .read_resources = domain_read_resources,
+ .set_resources = pci_domain_set_resources,
.enable_resources = domain_enable_resources,
.scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name,
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 0e0b2c30f3..3b5fd22969 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -84,7 +84,7 @@
#define CMP_CAP_MASK 0xff
void domain_enable_resources(struct device *dev);
-void domain_set_resources(struct device *dev);
+void domain_read_resources(struct device *dev);
void fam15_finalize(void *chip_info);
void set_warm_reset_flag(void);
int is_warm_reset(void);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 6c266232d8..c6fdc60073 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -414,7 +414,7 @@ void domain_enable_resources(struct device *dev)
do_agesawrapper(AMD_INIT_MID, "amdinitmid");
}
-void domain_set_resources(struct device *dev)
+void domain_read_resources(struct device *dev)
{
uint64_t uma_base = get_uma_base();
uint32_t uma_size = get_uma_size();
@@ -424,6 +424,8 @@ void domain_set_resources(struct device *dev)
uint64_t high_mem_useable;
int idx = 0x10;
+ pci_domain_read_resources(dev);
+
/* 0x0 -> 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
@@ -462,8 +464,6 @@ void domain_set_resources(struct device *dev)
uma_size / KiB);
}
}
-
- assign_resources(dev->link_list);
}
/*********************************************************************