diff options
| author | Martin Roth <gaumless@gmail.com> | 2018-04-11 16:35:08 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-13 16:50:41 +0000 |
| commit | 2c3e3ef654d5935e64e125b0c292313a41b53399 (patch) | |
| tree | 45de84862fa5ceb6c927003927008ae0934bf89d /src/soc/amd | |
| parent | 24231893d62616be3325c0e3f8c2f21b7d40ac65 (diff) | |
| download | coreboot-2c3e3ef654d5935e64e125b0c292313a41b53399.tar.xz | |
soc/amd/stoneyridge: add a romstage hook for mainboards
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/romstage.h | 21 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 8 |
2 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h new file mode 100644 index 0000000000..af30fd9844 --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_ROMSTAGE_H__ +#define __STONEYRIDGE_ROMSTAGE_H__ + +void mainboard_romstage_entry(int s3_resume); + +#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index cb24756baa..6c9726a02d 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -30,9 +30,15 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> +#include <soc/romstage.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> +void __attribute__((weak)) mainboard_romstage_entry(int s3_resume) +{ + /* By default, don't do anything */ +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -53,6 +59,8 @@ asmlinkage void car_stage_entry(void) console_init(); + mainboard_romstage_entry(s3_resume); + if (!s3_resume) { post_code(0x40); do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost"); |