summaryrefslogtreecommitdiff
path: root/src/soc/amd
diff options
context:
space:
mode:
authorFelix Held <felix.held@amd.corp-partner.google.com>2020-05-22 02:40:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-05-27 15:56:53 +0000
commitab114c96064422f92f8932f5d9fd837b259e93d6 (patch)
tree3d8a1d1b938673acd726941946aa28f79ae718dd /src/soc/amd
parent828ca06cdbedacb41f73dc70bf18262031f7ad90 (diff)
downloadcoreboot-ab114c96064422f92f8932f5d9fd837b259e93d6.tar.xz
soc/amd/picasso: add and use CPUIDs for older steppings
Change-Id: Ibe768ef7cd714c17fd5a296d9a3e5f963ae0ef01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41641 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/cpu.c7
-rw-r--r--src/soc/amd/picasso/include/soc/cpu.h8
-rw-r--r--src/soc/amd/picasso/soc_util.c8
3 files changed, 13 insertions, 10 deletions
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 88626971c5..55f9014c8f 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -115,9 +115,10 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x810f80 },
- { X86_VENDOR_AMD, PICASSO_CPUID },
- { X86_VENDOR_AMD, RAVEN2_CPUID },
+ { X86_VENDOR_AMD, PICASSO_B0_CPUID },
+ { X86_VENDOR_AMD, PICASSO_B1_CPUID },
+ { X86_VENDOR_AMD, RAVEN2_A0_CPUID },
+ { X86_VENDOR_AMD, RAVEN2_A1_CPUID },
{ 0, 0 },
};
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index a377c1ca42..d413c7293f 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -11,8 +11,10 @@ void picasso_init_cpus(struct device *dev);
int get_cpu_count(void);
void check_mca(void);
-#define RAVEN1_CPUID 0x00810f10
-#define PICASSO_CPUID 0x00810f81
-#define RAVEN2_CPUID 0x00820f01
+#define RAVEN1_B0_CPUID 0x00810f10
+#define PICASSO_B0_CPUID 0x00810f80
+#define PICASSO_B1_CPUID 0x00810f81
+#define RAVEN2_A0_CPUID 0x00820f00
+#define RAVEN2_A1_CPUID 0x00820f01
#endif /* __PICASSO_CPU_H__ */
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c
index 70cc578ec9..9c256ae703 100644
--- a/src/soc/amd/picasso/soc_util.c
+++ b/src/soc/amd/picasso/soc_util.c
@@ -85,25 +85,25 @@ static bool is_mystery_silicon(void)
static bool is_fam17_1x(void)
{
/* mask lower model number nibble and stepping */
- return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8;
+ return cpuid_eax(1) >> 8 == PICASSO_B1_CPUID >> 8;
}
static bool is_fam17_11(void)
{
/* only mask stepping */
- return cpuid_eax(1) >> 4 == RAVEN1_CPUID >> 4;
+ return cpuid_eax(1) >> 4 == RAVEN1_B0_CPUID >> 4;
}
static bool is_fam17_18(void)
{
/* only mask stepping */
- return cpuid_eax(1) >> 4 == PICASSO_CPUID >> 4;
+ return cpuid_eax(1) >> 4 == PICASSO_B1_CPUID >> 4;
}
static bool is_fam17_2x(void)
{
/* mask lower model number nibble and stepping */
- return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8;
+ return cpuid_eax(1) >> 8 == RAVEN2_A1_CPUID >> 8;
}
static bool is_fam17_20(void)