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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-10-05 18:03:19 -0600
committerMartin Roth <martinroth@google.com>2018-10-12 15:15:55 +0000
commitbba0439d09065a3646a85b37b90fcb83a19297c2 (patch)
treeb4cbb504f510bbbaaa3835534992b24d61595649 /src/soc/amd
parentfdefe96503b66ef18bc81f024dda0750eefb4727 (diff)
downloadcoreboot-bba0439d09065a3646a85b37b90fcb83a19297c2.tar.xz
amd/stoneyridge: Rearrange southbridge.h
Group definitions so they're near others of the same type, e.g. PCI, AcpiMmio, etc. Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h252
1 files changed, 130 insertions, 122 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 0aeb0fc12e..d25c90ba68 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -26,10 +26,10 @@
#include "chip.h"
#include <rules.h>
-/* PSP at D8F0 */
-#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
-#define PSP_BAR_ENABLES 0x48
-#define PSP_MAILBOX_BAR_EN 0x10
+/*
+ * AcpiMmio Region
+ * - fixed addresses offset from 0xfed80000
+ */
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_DECODE_EN 0x00
@@ -40,6 +40,10 @@
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
#define FORCE_STPCLK_RETRY BIT(24)
+
+#define PWR_RESET_CFG 0x10
+#define TOGGLE_ALL_PWR_GOOD BIT(1)
+
#define PM_SERIRQ_CONF 0x54
#define PM_SERIRQ_NUM_BITS_17 0x0000
#define PM_SERIRQ_NUM_BITS_18 0x0004
@@ -105,6 +109,114 @@
#define SPI_ROM_ALT_ENABLE BIT(0)
#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+/* FCH MISC Registers 0xfed80e00 */
+#define GPP_CLK_CNTRL 0
+#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8
+#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
+#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
+
+#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0
+#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
+#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1
+
+#define MISC_CGPLL_CONFIG1 0x08
+#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
+#define MISC_CGPLL_CONFIG3 0x10
+#define CG1PLL_REFDIV_SHIFT 0
+#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)
+#define CG1PLL_FBDIV_SHIFT 10
+#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)
+#define MISC_CGPLL_CONFIG4 0x14
+#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0
+#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
+#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16
+#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
+#define MISC_CGPLL_CONFIG5 0x18
+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8
+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
+#define MISC_CGPLL_CONFIG6 0x1c
+#define CG1PLL_LF_MODE_SHIFT 9
+#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
+#define MISC_CLK_CNTL1 0x40
+#define CG1PLL_FBDIV_TEST BIT(26)
+
+/* XHCI_PM Registers: 0xfed81c00 */
+#define XHCI_PM_INDIRECT_INDEX 0x48
+#define XHCI_PM_INDIRECT_DATA 0x4c
+#define XHCI_OVER_CURRENT_CONTROL 0x30
+#define USB_OC0 0
+#define USB_OC1 1
+#define USB_OC2 2
+#define USB_OC3 3
+#define USB_OC4 4
+#define USB_OC5 5
+#define USB_OC6 6
+#define USB_OC7 7
+#define USB_OC_DISABLE 0xf
+#define USB_OC_DISABLE_ALL 0xffff
+#define OC_PORT0_SHIFT 0
+#define OC_PORT1_SHIFT 4
+#define OC_PORT2_SHIFT 8
+#define OC_PORT3_SHIFT 12
+
+#define EHCI_OVER_CURRENT_CONTROL 0x70
+#define EHCI_HUB_CONFIG4 0x90
+#define DEBUG_PORT_SELECT_SHIFT 16
+#define DEBUG_PORT_ENABLE BIT(18)
+#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
+
+#define WIDEIO_RANGE_ERROR -1
+#define TOTAL_WIDEIO_PORTS 3
+
+/* FCH AOAC Registers 0xfed81e00 */
+#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
+#define FCH_AOAC_D3_CONTROL_I2C0 0x4a
+#define FCH_AOAC_D3_CONTROL_I2C1 0x4c
+#define FCH_AOAC_D3_CONTROL_I2C2 0x4e
+#define FCH_AOAC_D3_CONTROL_I2C3 0x50
+#define FCH_AOAC_D3_CONTROL_UART0 0x56
+#define FCH_AOAC_D3_CONTROL_UART1 0x58
+#define FCH_AOAC_D3_CONTROL_AMBA 0x62
+#define FCH_AOAC_D3_CONTROL_USB2 0x64
+#define FCH_AOAC_D3_CONTROL_USB3 0x6e
+/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
+#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
+#define FCH_AOAC_DEVICE_STATE BIT(2)
+#define FCH_AOAC_PWR_ON_DEV BIT(3)
+#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
+#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
+#define FCH_AOAC_SW_RST_B BIT(6)
+#define FCH_AOAC_IS_SW_CONTROL BIT(7)
+
+#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
+#define FCH_AOAC_D3_STATE_I2C0 0x4b
+#define FCH_AOAC_D3_STATE_I2C1 0x4d
+#define FCH_AOAC_D3_STATE_I2C2 0x4f
+#define FCH_AOAC_D3_STATE_I2C3 0x51
+#define FCH_AOAC_D3_STATE_UART0 0x57
+#define FCH_AOAC_D3_STATE_UART1 0x59
+#define FCH_AOAC_D3_STATE_AMBA 0x63
+#define FCH_AOAC_D3_STATE_USB2 0x65
+#define FCH_AOAC_D3_STATE_USB3 0x6f
+/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
+#define FCH_AOAC_PWR_RST_STATE BIT(0)
+#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
+#define FCH_AOAC_RST_B_STATE BIT(2)
+#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
+#define FCH_AOAC_D3COLD BIT(4)
+#define FCH_AOAC_CLK_OK_STATE BIT(5)
+#define FCH_AOAC_STAT0 BIT(6)
+#define FCH_AOAC_STAT1 BIT(7)
+
+#define PM1_LIMIT 16
+#define GPE0_LIMIT 28
+#define TOTAL_BITS(a) (8 * sizeof(a))
+
+/*
+ * PCI Config Space Definitions
+ */
+
+/* ISA Bridge D14F3 */
#define LPC_PCI_CONTROL 0x40
#define LEGACY_DMA_EN BIT(2)
@@ -159,6 +271,9 @@
#define LPC_WIDEIO0_ENABLE BIT(2)
#define DECODE_ALTERNATE_SIO_ENABLE BIT(1)
#define DECODE_SIO_ENABLE BIT(0)
+#define WIDEIO_RANGE_ERROR -1
+#define TOTAL_WIDEIO_PORTS 3
+
/* Assuming word access to higher word (register 0x4a) */
#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a
#define LPC_WIDEIO2_ENABLE_H BIT(9)
@@ -174,10 +289,8 @@
#define LPC_MEM_PORT1 0x4c
#define LPC_MEM_PORT0 0x60
-/*
- * Register 0x64 is 32-bit, composed by two 16-bit sub-registers.
- * For ease of access, each sub-register is declared separetely.
- */
+/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers.
+ For ease of access, each sub-register is declared separetely. */
#define LPC_WIDEIO_GENERIC_PORT 0x64
#define LPC_WIDEIO1_GENERIC_PORT 0x66
#define ROM_ADDRESS_RANGE1_START 0x68
@@ -199,11 +312,9 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90
-/*
- * LPC register 0xb8 is DWORD, here there are definitions for byte
- * access. For example, bits 31-24 are accessed through byte access
- * at register 0xbb ().
- */
+/* LPC register 0xb8 is DWORD, here there are definitions for byte
+ access. For example, bits 31-24 are accessed through byte access
+ at register 0xbb. */
#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8
#define SPI_FROM_HOST_PREFETCH_EN BIT(24)
#define SPI_FROM_USB_PREFETCH_EN BIT(23)
@@ -212,7 +323,7 @@
#define PREFETCH_EN_SPI_FROM_HOST BIT(0)
#define T_START_ENH BIT(3)
-/* SPI Controller */
+/* SPI Controller (base address in D14F3xA0) */
#define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31)
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
@@ -270,119 +381,16 @@
#define MISC_MISC_CLK_CNTL_1 0x40
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
+/* Platform Security Processor D8F0 */
+#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
+#define PSP_BAR_ENABLES 0x48
+#define PSP_MAILBOX_BAR_EN 0x10
+
/* IO 0xcf9 - Reset control port*/
#define FULL_RST BIT(3)
#define RST_CMD BIT(2)
#define SYS_RST BIT(1)
-/* PMx10 - Power Reset Config */
-#define PWR_RESET_CFG 0x10
-#define TOGGLE_ALL_PWR_GOOD BIT(1)
-
-/* XHCI_PM Registers: 0xfed81c00 */
-#define XHCI_PM_INDIRECT_INDEX 0x48
-#define XHCI_PM_INDIRECT_DATA 0x4c
-#define XHCI_OVER_CURRENT_CONTROL 0x30
-#define USB_OC0 0
-#define USB_OC1 1
-#define USB_OC2 2
-#define USB_OC3 3
-#define USB_OC4 4
-#define USB_OC5 5
-#define USB_OC6 6
-#define USB_OC7 7
-#define USB_OC_DISABLE 0xf
-#define USB_OC_DISABLE_ALL 0xffff
-#define OC_PORT0_SHIFT 0
-#define OC_PORT1_SHIFT 4
-#define OC_PORT2_SHIFT 8
-#define OC_PORT3_SHIFT 12
-
-#define EHCI_OVER_CURRENT_CONTROL 0x70
-#define EHCI_HUB_CONFIG4 0x90
-#define DEBUG_PORT_SELECT_SHIFT 16
-#define DEBUG_PORT_ENABLE BIT(18)
-#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
-
-#define WIDEIO_RANGE_ERROR -1
-#define TOTAL_WIDEIO_PORTS 3
-
-/* FCH AOAC Registers 0xfed81e00 */
-#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
-#define FCH_AOAC_D3_CONTROL_I2C0 0x4a
-#define FCH_AOAC_D3_CONTROL_I2C1 0x4c
-#define FCH_AOAC_D3_CONTROL_I2C2 0x4e
-#define FCH_AOAC_D3_CONTROL_I2C3 0x50
-#define FCH_AOAC_D3_CONTROL_UART0 0x56
-#define FCH_AOAC_D3_CONTROL_UART1 0x58
-#define FCH_AOAC_D3_CONTROL_AMBA 0x62
-#define FCH_AOAC_D3_CONTROL_USB2 0x64
-#define FCH_AOAC_D3_CONTROL_USB3 0x6e
-/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
-#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
-#define FCH_AOAC_DEVICE_STATE BIT(2)
-#define FCH_AOAC_PWR_ON_DEV BIT(3)
-#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
-#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
-#define FCH_AOAC_SW_RST_B BIT(6)
-#define FCH_AOAC_IS_SW_CONTROL BIT(7)
-
-#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
-#define FCH_AOAC_D3_STATE_I2C0 0x4b
-#define FCH_AOAC_D3_STATE_I2C1 0x4d
-#define FCH_AOAC_D3_STATE_I2C2 0x4f
-#define FCH_AOAC_D3_STATE_I2C3 0x51
-#define FCH_AOAC_D3_STATE_UART0 0x57
-#define FCH_AOAC_D3_STATE_UART1 0x59
-#define FCH_AOAC_D3_STATE_AMBA 0x63
-#define FCH_AOAC_D3_STATE_USB2 0x65
-#define FCH_AOAC_D3_STATE_USB3 0x6f
-/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
-#define FCH_AOAC_PWR_RST_STATE BIT(0)
-#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
-#define FCH_AOAC_RST_B_STATE BIT(2)
-#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
-#define FCH_AOAC_D3COLD BIT(4)
-#define FCH_AOAC_CLK_OK_STATE BIT(5)
-#define FCH_AOAC_STAT0 BIT(6)
-#define FCH_AOAC_STAT1 BIT(7)
-
-#define PM1_LIMIT 16
-#define GPE0_LIMIT 28
-#define TOTAL_BITS(a) (8 * sizeof(a))
-
-/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */
-#define GPP_CLK_CNTRL 0
-#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8
-#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
-#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
-
-#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0
-#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
-#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1
-
-/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */
-#define MISC_CGPLL_CONFIG1 0x08
-#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
-#define MISC_CGPLL_CONFIG3 0x10
-#define CG1PLL_REFDIV_SHIFT 0
-#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)
-#define CG1PLL_FBDIV_SHIFT 10
-#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)
-#define MISC_CGPLL_CONFIG4 0x14
-#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0
-#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
-#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16
-#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
-#define MISC_CGPLL_CONFIG5 0x18
-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8
-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
-#define MISC_CGPLL_CONFIG6 0x1c
-#define CG1PLL_LF_MODE_SHIFT 9
-#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
-#define MISC_CLK_CNTL1 0x40
-#define CG1PLL_FBDIV_TEST BIT(26)
-
struct stoneyridge_aoac {
int enable;
int status;