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| author | Marc Jones <marc.jones@scarletltd.com> | 2018-05-25 20:53:44 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2018-06-01 02:52:19 +0000 |
| commit | 9022b9d2aaa2421a069c26ac656b3954138a0674 (patch) | |
| tree | 20565c12b48e3b47331f60b03c4f7a1f9303ddc9 /src/soc/amd | |
| parent | f743728e9fe05705bbac01978368cdd8ddcf2af6 (diff) | |
| download | coreboot-9022b9d2aaa2421a069c26ac656b3954138a0674.tar.xz | |
soc/amd/stoneyridge: Add ACPI device name lookup
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup
function.
BUG=b:80280671
TEST=Add ACPI method to specific GPP bridge. Boot and verify method
with ACPI dump.
Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/26698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 3b73a054b8..9ca2db7e85 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -82,6 +82,18 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { + case PCIE0_DEVFN: + return "PBR4"; + case PCIE1_DEVFN: + return "PBR5"; + case PCIE2_DEVFN: + return "PBR6"; + case PCIE3_DEVFN: + return "PBR7"; + case PCIE4_DEVFN: + return "PBR8"; + case HDA1_DEVFN: + return "AZHD"; case EHCI1_DEVFN: return "EHC0"; case LPC_DEVFN: |