diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-08-03 10:37:28 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-06 01:09:04 +0000 |
| commit | bb18b43065f678b8c9987c75075adb9ed25900b3 (patch) | |
| tree | 3ac88a84967948b54686372d30f4587e82e17d32 /src/soc/amd | |
| parent | cea849328599c98219ff78cfb83083573aa80f77 (diff) | |
| download | coreboot-bb18b43065f678b8c9987c75075adb9ed25900b3.tar.xz | |
soc/amd/stoneyridge: Disable SATA based on devicetree setting
Grunt boards don't use SATA, so it should be disabled to save power.
Check if SATA is enabled in devicetree, and enable/disable the device
based on that setting.
BUG=b:112139043
TEST=Buil and boot grunt, checked the absence of SATA PCI.
Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/BiosCallOuts.c | 28 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 24 |
2 files changed, 35 insertions, 17 deletions
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 430dc45ba3..9f74e8fc9f 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -53,6 +53,7 @@ AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + const struct device *dev = dev_find_slot(0, SATA_DEVFN); if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -67,19 +68,22 @@ AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) /* SATA configuration */ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: + if (dev && dev->enabled) { + switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } + } else FchParams_env->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams_env->Sata.SataIdeMode = TRUE; - break; - } /* Platform updates */ platform_FchParams_env(FchParams_env); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 63d8806fd0..f098c1c329 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -72,18 +72,32 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { + const struct device *dev = dev_find_slot(0, SATA_DEVFN); params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); + if (dev && dev->enabled) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } } void SetFchEnvParams(FCH_INTERFACE *params) { + const struct device *dev = dev_find_slot(0, SATA_DEVFN); params->AzaliaController = AzEnable; params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); + if (dev && dev->enabled) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } } void SetFchMidParams(FCH_INTERFACE *params) |