diff options
author | Martin Roth <martinroth@google.com> | 2016-11-11 10:31:48 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-11-17 17:57:09 +0100 |
commit | b9e8ad8f681042bae5f3da420719f64b2fd75141 (patch) | |
tree | 9b1de338f251fd8b049d99c45ff8df4f1d35238c /src/soc/broadcom/cygnus/ddr_init.c | |
parent | 1cf5b87f48668055e531a13c143abf697934dc80 (diff) | |
download | coreboot-b9e8ad8f681042bae5f3da420719f64b2fd75141.tar.xz |
soc/broadcom/cygnus: Update DDR Kconfig
The DDR speed Kconfig symbols needed to either be added to the Kconfig
tree, or have the code associated with them removed. I chose to add
the symbols.
- Add symbols for DDR333 - DDR667 to cygnus Kconfig. These should be
selected by the mainboard.
- Rename symbols from DDRXXX to CYGNUS_DDRXXX to match the existing
CYGNUS_DDR800 symbol.
- Rename the non Kconfig #define CONFIG_DRAM_FREQ to CYGNUS_DRAM_FREQ
because having other #defines look like Kconfig symbols is confusing.
- Change #ifdef CONFIG_DDRXXX to use IS_ENABLED
Change-Id: I3f5957a595072434c21af0002d57ac49b48b1e43
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'src/soc/broadcom/cygnus/ddr_init.c')
-rw-r--r-- | src/soc/broadcom/cygnus/ddr_init.c | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index bc39b2ae33..b6bbf4a86f 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -29,24 +29,24 @@ extern unsigned int ddr2_init_tab_1066[]; extern unsigned int ddr2_mode_reg_tab[]; #endif -#ifdef CONFIG_DDR333 -#define CONFIG_DRAM_FREQ 333 +#if IS_ENABLED(CONFIG_CYGNUS_DDR333) +#define CYGNUS_DRAM_FREQ 333 extern unsigned int ddr3_init_tab_667[]; #endif -#ifdef CONFIG_DDR400 -#define CONFIG_DRAM_FREQ 400 +#if IS_ENABLED(CONFIG_CYGNUS_DDR400) +#define CYGNUS_DRAM_FREQ 400 extern unsigned int ddr3_init_tab_800[]; #endif -#ifdef CONFIG_DDR533 -#define CONFIG_DRAM_FREQ 533 +#if IS_ENABLED(CONFIG_CYGNUS_DDR533) +#define CYGNUS_DRAM_FREQ 533 extern unsigned int ddr3_init_tab_1066[]; #endif -#ifdef CONFIG_DDR667 -#define CONFIG_DRAM_FREQ 667 +#if IS_ENABLED(CONFIG_CYGNUS_DDR667) +#define CYGNUS_DRAM_FREQ 667 extern unsigned int ddr3_init_tab_1333[]; #endif #if IS_ENABLED(CONFIG_CYGNUS_DDR800) -#define CONFIG_DRAM_FREQ 800 +#define CYGNUS_DRAM_FREQ 800 extern unsigned int ddr3_init_tab_1600[]; #endif @@ -485,10 +485,10 @@ int is_ddr_32bit(void) static uint32_t get_ddr_clock(uint32_t sku_id, int ddr_type) { -#ifdef CONFIG_DRAM_FREQ - return CONFIG_DRAM_FREQ; +#ifdef CYGNUS_DRAM_FREQ + return CYGNUS_DRAM_FREQ; #else - #error Please set DDR frequency (CONFIG_DRAM_FREQ must be set) + #error Please set DDR frequency (CYGNUS_DRAM_FREQ must be set) #endif } @@ -1461,28 +1461,27 @@ void ddr_init2(void) if (ddr_type) { /* DDR3 */ switch(ddr_clk) { -#ifdef CONFIG_DDR333 +#if IS_ENABLED(CONFIG_CYGNUS_DDR333) case 333: ddr_init_regs(ddr3_init_tab_667); break; #endif -#ifdef CONFIG_DDR400 +#if IS_ENABLED(CONFIG_CYGNUS_DDR400) case 400: ddr_init_regs(ddr3_init_tab_800); break; #endif -#ifdef CONFIG_DDR533 +#if IS_ENABLED(CONFIG_CYGNUS_DDR533) case 533: ddr_init_regs(ddr3_init_tab_1066); break; #endif -#ifdef CONFIG_DDR667 +#if IS_ENABLED(CONFIG_CYGNUS_DDR667) case 667: ddr_init_regs(ddr3_init_tab_1333); break; #endif -#if (defined(CONFIG_DDR750) || IS_ENABLED(CONFIG_CYGNUS_DDR800)) - case 750: +#if IS_ENABLED(CONFIG_CYGNUS_DDR800) case 800: ddr_init_regs(ddr3_init_tab_1600); break; |