diff options
| author | Icarus Chau <ichau@broadcom.com> | 2015-04-07 16:09:24 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 09:03:46 +0200 |
| commit | be47636de01bed851a6b008067638ccb48343207 (patch) | |
| tree | d287ede000e0e393b1a99d1a37c749b3fb4719ad /src/soc/broadcom/cygnus/ddr_init.c | |
| parent | bcdbdc6761768037a98514a8fa4364d1f4124e93 (diff) | |
| download | coreboot-be47636de01bed851a6b008067638ccb48343207.tar.xz | |
broadcom/cygnus: Enable DDR auto self-refresh
Enable auto entry and auto exit self-refresh.
Configure entry idle time to 16x long count sequences.
Where a long count sequence is 1024 cycles.
The idle entry configuration is based on 32x of the DLL lock time (512 cycles).
A conservative setting to help minimize self-refresh enter/exit thrashing.
BUG=chrome-os-partner:36456
BRANCH=broadcom-firmware
TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR,
print on console:
sdram initialization is completed.
test ddr start from 0x60000000 to 0x80000000
...
test ddr end: fail=0
Translation table is @ 02004000
Mapping address range [0x00000000:0x00000000) as uncached
Change-Id: Ibad220429fd52ead2933db03bec1a555f9385e53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3768f82ca268fb854f8c4753916518a1efdf887d
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212125
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Signed-off-by: Icarus Chau <ichau@broadcom.com>
Original-Change-Id: Icac1e12745d048b32e1804a546f6b49c8b5953c0
Original-Reviewed-on: https://chromium-review.googlesource.com/265862
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/9930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/broadcom/cygnus/ddr_init.c')
| -rwxr-xr-x | src/soc/broadcom/cygnus/ddr_init.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 27a981ee66..9aac58f7e9 100755 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -1490,6 +1490,27 @@ void ddr_init2(void) } } +#if CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE +#if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff) + /* Enable auto self-refresh */ + reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + + reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58, + DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); +#else + #error DDR_AUTO_SELF_REFRESH_IDLE_COUNT out of range +#endif +#else + /* Disable auto-self refresh */ + reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57, + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58, + 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R ); +#endif + /* Start the DDR */ reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01); |