broadcom/cygnus: Enable DDR auto self-refresh

Enable auto entry and auto exit self-refresh.
Configure entry idle time to 16x long count sequences.
Where a long count sequence is 1024 cycles.
The idle entry configuration is based on 32x of the DLL lock time (512 cycles).
A conservative setting to help minimize self-refresh enter/exit thrashing.

BUG=chrome-os-partner:36456
BRANCH=broadcom-firmware
TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR,
print on console:

sdram initialization is completed.
test ddr start from 0x60000000 to 0x80000000
...
test ddr end: fail=0
Translation table is @ 02004000
Mapping address range [0x00000000:0x00000000) as uncached

Change-Id: Ibad220429fd52ead2933db03bec1a555f9385e53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3768f82ca268fb854f8c4753916518a1efdf887d
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212125
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Signed-off-by: Icarus Chau <ichau@broadcom.com>
Original-Change-Id: Icac1e12745d048b32e1804a546f6b49c8b5953c0
Original-Reviewed-on: https://chromium-review.googlesource.com/265862
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/9930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 66 insertions, 0 deletions

diff --git a/src/soc/broadcom/cygnus/include/soc/config.h b/src/soc/broadcom/cygnus/include/soc/config.h
index 7511827338..0ba09e372b 100755
--- a/src/soc/broadcom/cygnus/include/soc/config.h
+++ b/src/soc/broadcom/cygnus/include/soc/config.h
@@ -29,4 +29,8 @@
 #else
 #define SDI_NUM_ROWS			65536
 #endif
+
+/* Idle count (in units of 1024 cycles) before auto entering self-refresh  */
+#define DDR_AUTO_SELF_REFRESH_IDLE_COUNT	16
+
 #endif /* __SOC_BROADCOM_CYGNUS_CONFIG_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h b/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
index 80cd9690e4..32668d1d86 100644
--- a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
+++ b/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
@@ -114,6 +114,68 @@
 #define DDR_DENALI_CTL_56_DATAMASK 0xffffffff
 #define DDR_DENALI_CTL_56_RDWRMASK 0x00000000
 #define DDR_DENALI_CTL_56_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57 0x180100e4
+#define DDR_DENALI_CTL_57_BASE 0x0e4
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_L 26
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R 24
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_WIDTH 3
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_L 18
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R 16
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_WIDTH 3
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_L 11
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_R 8
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_WIDTH 4
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57__LP_STATE_L 5
+#define DDR_DENALI_CTL_57__LP_STATE_R 0
+#define DDR_DENALI_CTL_57__LP_STATE_WIDTH 6
+#define DDR_DENALI_CTL_57__LP_STATE_RESETVALUE 0x20
+#define DDR_DENALI_CTL_57__RESERVED_0_L 31
+#define DDR_DENALI_CTL_57__RESERVED_0_R 27
+#define DDR_DENALI_CTL_57__RESERVED_1_L 23
+#define DDR_DENALI_CTL_57__RESERVED_1_R 19
+#define DDR_DENALI_CTL_57__RESERVED_2_L 15
+#define DDR_DENALI_CTL_57__RESERVED_2_R 12
+#define DDR_DENALI_CTL_57__RESERVED_3_L 7
+#define DDR_DENALI_CTL_57__RESERVED_3_R 6
+#define DDR_DENALI_CTL_57__RESERVED_L 31
+#define DDR_DENALI_CTL_57__RESERVED_R 27
+#define DDR_DENALI_CTL_57_WIDTH 27
+#define DDR_DENALI_CTL_57__WIDTH 27
+#define DDR_DENALI_CTL_57_ALL_L 26
+#define DDR_DENALI_CTL_57_ALL_R 0
+#define DDR_DENALI_CTL_57__ALL_L 26
+#define DDR_DENALI_CTL_57__ALL_R 0
+#define DDR_DENALI_CTL_57_DATAMASK 0x07070f3f
+#define DDR_DENALI_CTL_57_RDWRMASK 0xf8f8f0c0
+#define DDR_DENALI_CTL_57_RESETVALUE 0x20
+#define DDR_DENALI_CTL_58 0x180100e8
+#define DDR_DENALI_CTL_58_BASE 0x0e8
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_L 31
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R 24
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_WIDTH 8
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_RESETVALUE 0x00
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_L 19
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_R 8
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_WIDTH 12
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_RESETVALUE 0x000
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_L 1
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_R 0
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_WIDTH 2
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_RESETVALUE 0x0
+#define DDR_DENALI_CTL_58__RESERVED_L 23
+#define DDR_DENALI_CTL_58__RESERVED_R 20
+#define DDR_DENALI_CTL_58_WIDTH 32
+#define DDR_DENALI_CTL_58__WIDTH 32
+#define DDR_DENALI_CTL_58_ALL_L 31
+#define DDR_DENALI_CTL_58_ALL_R 0
+#define DDR_DENALI_CTL_58__ALL_L 31
+#define DDR_DENALI_CTL_58__ALL_R 0
+#define DDR_DENALI_CTL_58_DATAMASK 0xff0fff03
+#define DDR_DENALI_CTL_58_RDWRMASK 0x00f000fc
+#define DDR_DENALI_CTL_58_RESETVALUE 0x0
 
 #define DDR_DENALI_CTL_175 0x180102bc
 #define DDR_DENALI_CTL_175_BASE 0x2bc