spi: Define and use spi_ctrlr structure

1. Define a new structure spi_ctrlr that allows platforms to define
callbacks for spi operations (claim bus, release bus, transfer).
2. Add a new member (pointer to spi_ctrlr structure) in spi_slave
structure which will be initialized by call to spi_setup_slave.
3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c
which will make appropriate calls to ctrlr functions.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17684
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 47 insertions, 40 deletions

diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c
index 810f2c266c..e597efced9 100644
--- a/src/soc/broadcom/cygnus/spi.c
+++ b/src/soc/broadcom/cygnus/spi.c
@@ -96,42 +96,6 @@ static struct qspi_priv *to_qspi_slave(const struct spi_slave *slave)
 	return &qspi_slave;
 }
 
-int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
-{
-	struct qspi_priv *priv = &qspi_slave;
-	unsigned int spbr;
-
-	slave->bus = bus;
-	slave->cs = cs;
-
-	priv->max_hz = QSPI_MAX_HZ;
-	priv->spi_mode = QSPI_MODE;
-	priv->reg = (void *)(IPROC_QSPI_BASE);
-	priv->mspi_enabled = 0;
-	priv->bus_claimed = 0;
-
-	/* MSPI: Basic hardware initialization */
-	REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0);
-	REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0);
-	REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
-	REG_WR(priv->reg + MSPI_ENDQP_REG, 0);
-	REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
-
-	/* MSPI: SCK configuration */
-	spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1;
-	REG_WR(priv->reg + MSPI_SPCR0_LSB_REG,
-	       MAX(MIN(spbr, SPBR_MAX), SPBR_MIN));
-
-	/* MSPI: Mode configuration (8 bits by default) */
-	priv->mspi_16bit = 0;
-	REG_WR(priv->reg + MSPI_SPCR0_MSB_REG,
-	       0x80 |			/* Master */
-	       (8 << 2) |		/* 8 bits per word */
-	       (priv->spi_mode & 3));	/* mode: CPOL / CPHA */
-
-	return 0;
-}
-
 static int mspi_enable(struct qspi_priv *priv)
 {
 	struct stopwatch sw;
@@ -156,7 +120,7 @@ static int mspi_enable(struct qspi_priv *priv)
 	return 0;
 }
 
-int spi_claim_bus(const struct spi_slave *slave)
+static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 {
 	struct qspi_priv *priv = to_qspi_slave(slave);
 
@@ -175,7 +139,7 @@ int spi_claim_bus(const struct spi_slave *slave)
 	return 0;
 }
 
-void spi_release_bus(const struct spi_slave *slave)
+static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 {
 	struct qspi_priv *priv = to_qspi_slave(slave);
 
@@ -189,8 +153,8 @@ void spi_release_bus(const struct spi_slave *slave)
 #define RXRAM_8B(p, i)	(REG_RD((p)->reg + MSPI_RXRAM_REG + \
 				((((i) << 1) + 1) << 2)) & 0xff)
 
-int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout,
-	     void *din, size_t bytesin)
+static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
+			   size_t bytesout, void *din, size_t bytesin)
 {
 	struct qspi_priv *priv = to_qspi_slave(slave);
 	const u8 *tx = (const u8 *)dout;
@@ -311,6 +275,49 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout,
 	return 0;
 }
 
+static const struct spi_ctrlr spi_ctrlr = {
+	.claim_bus = spi_ctrlr_claim_bus,
+	.release_bus = spi_ctrlr_release_bus,
+	.xfer = spi_ctrlr_xfer,
+};
+
+int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
+{
+	struct qspi_priv *priv = &qspi_slave;
+	unsigned int spbr;
+
+	slave->bus = bus;
+	slave->cs = cs;
+	slave->ctrlr = &spi_ctrlr;
+
+	priv->max_hz = QSPI_MAX_HZ;
+	priv->spi_mode = QSPI_MODE;
+	priv->reg = (void *)(IPROC_QSPI_BASE);
+	priv->mspi_enabled = 0;
+	priv->bus_claimed = 0;
+
+	/* MSPI: Basic hardware initialization */
+	REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0);
+	REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0);
+	REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
+	REG_WR(priv->reg + MSPI_ENDQP_REG, 0);
+	REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
+
+	/* MSPI: SCK configuration */
+	spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1;
+	REG_WR(priv->reg + MSPI_SPCR0_LSB_REG,
+	       MAX(MIN(spbr, SPBR_MAX), SPBR_MIN));
+
+	/* MSPI: Mode configuration (8 bits by default) */
+	priv->mspi_16bit = 0;
+	REG_WR(priv->reg + MSPI_SPCR0_MSB_REG,
+	       0x80 |			/* Master */
+	       (8 << 2) |		/* 8 bits per word */
+	       (priv->spi_mode & 3));	/* mode: CPOL / CPHA */
+
+	return 0;
+}
+
 unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
 {
 	return min(65535, buf_len);