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author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-04-11 11:40:55 +0200 |
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committer | Patrick Rudolph <siro@das-labor.org> | 2018-07-10 07:07:09 +0000 |
commit | 88f81af1ef0d74ca2be865454cc801efe32a88af (patch) | |
tree | 997d9a0b703bbb82f9e7666dd06984bf215c928d /src/soc/cavium/cn81xx/Makefile.inc | |
parent | ae15fec0b8ca7578ee56e2d1d9579922bb1ec0b6 (diff) | |
download | coreboot-88f81af1ef0d74ca2be865454cc801efe32a88af.tar.xz |
soc/cavium: Add secondary CPU support
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/Makefile.inc')
-rw-r--r-- | src/soc/cavium/cn81xx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 2e12b0137c..16aa4ff2ab 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -62,6 +62,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += sdram.c ramstage-y += soc.c ramstage-y += cpu.c +ramstage-y += cpu_secondary.S # BDK coreboot interface ramstage-y += ../common/bdk-coreboot.c |