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author | David Hendricks <dhendricks@fb.com> | 2017-12-01 20:49:48 -0800 |
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committer | Patrick Rudolph <siro@das-labor.org> | 2018-07-10 07:01:57 +0000 |
commit | 8cbd569f74d8929387730e45b0d6e993b1365c02 (patch) | |
tree | ca6414a4d81e37280887b0da0f1a6120a50f0a3a /src/soc/cavium/cn81xx/Makefile.inc | |
parent | 03d31427338ba59d3a354ac1beb3b0c153471768 (diff) | |
download | coreboot-8cbd569f74d8929387730e45b0d6e993b1365c02.tar.xz |
cavium: Add CN81xx SoC and eval board support
This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/Makefile.inc')
-rw-r--r-- | src/soc/cavium/cn81xx/Makefile.inc | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc new file mode 100644 index 0000000000..d265c19bb8 --- /dev/null +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -0,0 +1,70 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_CAVIUM_CN81XX),y) + +# bootblock +bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock_custom.S +bootblock-y += bootblock.c +bootblock-y += twsi.c +bootblock-y += clock.c +bootblock-y += gpio.c +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += uart.c +bootblock-y += cpu.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_DRIVERS_UART) += uart.c +endif + +################################################################################ +# romstage + +romstage-y += twsi.c +romstage-y += clock.c +romstage-y += gpio.c +romstage-y += timer.c +romstage-y += spi.c +romstage-y += uart.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-< += cpu.c + +romstage-y += sdram.c +romstage-y += ../common/cbmem.c +# BDK coreboot interface +romstage-y += ../common/bdk-coreboot.c + + +################################################################################ +# ramstage + +ramstage-y += twsi.c +ramstage-y += clock.c +ramstage-y += gpio.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += sdram.c +ramstage-y += soc.c +ramstage-y += cpu.c + +# BDK coreboot interface +ramstage-y += ../common/bdk-coreboot.c + + +CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include + +endif |