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authorNico Huber <nico.h@gmx.de>2018-10-06 18:39:24 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-17 12:02:35 +0000
commit10d7845f0946b41faeac6f08b16f99051bc38660 (patch)
tree10fbaff5ce80db652216abd9e97f5b545ceaaacc /src/soc/cavium/cn81xx/Makefile.inc
parent773cc1b413af580db3dedebafe4cdfdf7808aa29 (diff)
downloadcoreboot-10d7845f0946b41faeac6f08b16f99051bc38660.tar.xz
soc/cavium/cn81xx: Drop dead do_soft_reset() implementation
Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/cavium/cn81xx/Makefile.inc')
-rw-r--r--src/soc/cavium/cn81xx/Makefile.inc4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index d212715d80..ede7d73f71 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -25,7 +25,6 @@ bootblock-y += timer.c
bootblock-y += spi.c
bootblock-y += uart.c
bootblock-y += cpu.c
-bootblock-y += reset.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
@@ -40,7 +39,6 @@ verstage-y += timer.c
verstage-y += spi.c
verstage-$(CONFIG_DRIVERS_UART) += uart.c
verstage-y += cbmem.c
-verstage-y += reset.c
################################################################################
# romstage
@@ -53,7 +51,6 @@ romstage-y += spi.c
romstage-y += uart.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += cbmem.c
-romstage-y += reset.c
romstage-y += sdram.c
romstage-y += mmu.c
@@ -74,7 +71,6 @@ ramstage-y += cpu.c
ramstage-y += cpu_secondary.S
ramstage-y += ecam0.c
ramstage-y += cbmem.c
-ramstage-y += reset.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c