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author | David Hendricks <dhendricks@fb.com> | 2017-12-01 20:49:48 -0800 |
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committer | Patrick Rudolph <siro@das-labor.org> | 2018-07-10 07:01:57 +0000 |
commit | 8cbd569f74d8929387730e45b0d6e993b1365c02 (patch) | |
tree | ca6414a4d81e37280887b0da0f1a6120a50f0a3a /src/soc/cavium/cn81xx/soc.c | |
parent | 03d31427338ba59d3a354ac1beb3b0c153471768 (diff) | |
download | coreboot-8cbd569f74d8929387730e45b0d6e993b1365c02.tar.xz |
cavium: Add CN81xx SoC and eval board support
This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/soc.c')
-rw-r--r-- | src/soc/cavium/cn81xx/soc.c | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c new file mode 100644 index 0000000000..03f9122404 --- /dev/null +++ b/src/soc/cavium/cn81xx/soc.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. <support@cavium.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. + */ + +#include <bootmode.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/sdram.h> +#include <soc/timer.h> +#include <stddef.h> +#include <stdlib.h> +#include <string.h> +#include <symbols.h> +#include <libbdk-boot/bdk-boot.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB); +} + +static void soc_init(device_t dev) +{ + /* Init ECAM, MDIO, PEM, PHY, QLM ... */ + bdk_boot(); + + /* TODO: additional trustzone init */ +} + +static void soc_final(device_t dev) +{ + watchdog_disable(0); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, + .final = soc_final, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_cavium_cn81xx_ops = { + CHIP_NAME("SOC Cavium CN81XX") + .enable_dev = enable_soc_dev, +}; |