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authorJulius Werner <jwerner@chromium.org>2019-12-02 22:03:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-04 14:11:17 +0000
commit55009af42c39f413c49503670ce9bc2858974962 (patch)
tree099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/cavium/cn81xx/timer.c
parent1c371572188a90ea16275460dd4ab6bf9966350b (diff)
downloadcoreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/cavium/cn81xx/timer.c')
-rw-r--r--src/soc/cavium/cn81xx/timer.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c
index bd67d8a888..be15b9be8e 100644
--- a/src/soc/cavium/cn81xx/timer.c
+++ b/src/soc/cavium/cn81xx/timer.c
@@ -123,7 +123,7 @@ void init_timer(void)
write32(&gti->cc_cntrate, ((1ULL << 32) * tickrate) / sclk);
/* Enable the counter */
- setbits_le32(&gti->cc_cntcr, GTI_CC_CNTCR_EN);
+ setbits32(&gti->cc_cntcr, GTI_CC_CNTCR_EN);
//u32 u = (CNTPS_CTL_EL1_IMASK | CNTPS_CTL_EL1_EN);
//BDK_MSR(CNTPS_CTL_EL1, u);
@@ -172,11 +172,11 @@ void watchdog_set(const size_t index, unsigned int timeout_ms)
printk(BIOS_DEBUG, "Watchdog: Set to expire %llu SCLK cycles\n",
timeout_wdog << 18);
- clrsetbits_le64(&timer->cwd_wdog[index],
- (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) |
- (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT),
- (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) |
- (3 << GTI_CWD_WDOG_MODE_SHIFT));
+ clrsetbits64(&timer->cwd_wdog[index],
+ (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) |
+ (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT),
+ (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) |
+ (3 << GTI_CWD_WDOG_MODE_SHIFT));
}
/**