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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2018-10-16 20:38:14 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:21:05 +0000 |
| commit | e9e08ceb3c89c5d1c4bfea1e403d061aea237a2b (patch) | |
| tree | 5bb47bd3a57787e0c15600babfbddb67bf233d6b /src/soc/cavium/cn81xx | |
| parent | 3ee54bbf9413b5e174e65eff14769bdd2f5a3203 (diff) | |
| download | coreboot-e9e08ceb3c89c5d1c4bfea1e403d061aea237a2b.tar.xz | |
vendorcode/intel/fsp/icelake: Add icelake FSP header file template
icelake FSP is still under development and hence the FSP header files
and binaries are not available on github. Meanwhile add basic header
files required to compile the SoC and mainboard with FSP2.0.
BUG=None
BRANCH=None
TEST=Build for icelake_rvp board successfull.
Change-Id: I9ab8f180b572ec553e7531f7483d091f6897c462
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/29163
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium/cn81xx')
0 files changed, 0 insertions, 0 deletions