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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-04-17 13:47:55 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-07-19 13:57:24 +0000
commitd0c6797e796af155cd435ed344958dbb9c418a86 (patch)
tree57bc66cdea7783d3d6025d7df458fc790f4bece6 /src/soc/cavium/common
parent02c08147645d37e8d21f89b62cb7029be7543bd6 (diff)
downloadcoreboot-d0c6797e796af155cd435ed344958dbb9c418a86.tar.xz
soc/cavium: Add PCI support
* Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium/common')
-rw-r--r--src/soc/cavium/common/pci/chip.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h
new file mode 100644
index 0000000000..0d0d33f59d
--- /dev/null
+++ b/src/soc/cavium/common/pci/chip.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H
+#define __SOC_CAVIUM_COMMON_PCI_CHIP_H
+
+struct soc_cavium_common_pci_config {
+ /**
+ * Mark the PCI device as secure.
+ * It will be visible from EL3, but hidden in EL2-0.
+ */
+ u8 secure;
+};
+
+#endif /* __SOC_CAVIUM_COMMON_PCI_CHIP_H */