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| author | li feng <li1.feng@intel.com> | 2020-03-12 16:09:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-16 14:46:31 +0000 |
| commit | 2cf9d3883cc09aa2410135b87d715f47608ae38d (patch) | |
| tree | b7aff1e00851ff70f058ecdb316ceb074c2c7b88 /src/soc/cavium | |
| parent | b159d443dd6e2bd977d30b3cb5db86b38430c1ea (diff) | |
| download | coreboot-2cf9d3883cc09aa2410135b87d715f47608ae38d.tar.xz | |
soc/intel/tigerlake: Support ISH
Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree
BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/cavium')
0 files changed, 0 insertions, 0 deletions