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author | Furquan Shaikh <furquan@google.com> | 2020-05-11 14:28:13 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 08:41:20 +0000 |
commit | 70063ff565cbc9fafd54dc3efeb313d1789ce9eb (patch) | |
tree | 212be0bc58f85d208e631b893b66e6482ffef385 /src/soc/cavium | |
parent | 785a3b4a6fa7c0d2597d3322e8c0394d51c9c41a (diff) | |
download | coreboot-70063ff565cbc9fafd54dc3efeb313d1789ce9eb.tar.xz |
soc/amd/common/block: Add support for configuring eSPI connection to slave
This change adds a helper function espi_setup() which allows SoCs to
configure connection to slave. Most of the configuration is dependent
upon mainboard settings in espi_config done as part of the device
tree. The general flow for setup involves the following steps:
1. Set initial configuration (lowest operating frequency and single mode).
2. Perform in-band reset and set initial configuration since the
settings would be lost by the reset.
3. Read slave capabilities.
4. Set slave configuration based on mainboard settings.
5. Perform eSPI host controller configuration to match the slave
configuration and set polarities for VW interrupts.
6. Perform VW channel setup and deassert PLTRST#.
7. Perform peripheral channel setup.
8. Perform OOB channel setup.
9. Perform flash channel setup.
10. Enable subtractive decoding if requested by mainboard.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I872ec09cd92e9bb53f22e38d2773f3491355279e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41272
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium')
0 files changed, 0 insertions, 0 deletions