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authorElyes HAOUAS <ehaouas@noos.fr>2019-03-29 17:12:15 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 10:01:36 +0000
commitcd4fe0f718cfc49e5d58f1770e23cd065a26241e (patch)
treea1b335fc76f89e79480456e3c6cd1672f4eefb2c /src/soc/cavium
parent351e3e520ba71b4aafaf930af37f78b71c1d7251 (diff)
downloadcoreboot-cd4fe0f718cfc49e5d58f1770e23cd065a26241e.tar.xz
src: include <assert.h> when appropriate
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/cavium')
-rw-r--r--src/soc/cavium/cn81xx/ecam0.c1
-rw-r--r--src/soc/cavium/cn81xx/twsi.c1
-rw-r--r--src/soc/cavium/common/ecam.c1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c
index 6e0cb9c731..6659cdf3bc 100644
--- a/src/soc/cavium/cn81xx/ecam0.c
+++ b/src/soc/cavium/cn81xx/ecam0.c
@@ -23,7 +23,6 @@
#include <soc/addressmap.h>
#include <soc/cavium/common/pci/chip.h>
#include <soc/ecam.h>
-#include <assert.h>
#define CAVM_PCCPF_XXX_VSEC_CTL 0x108
#define CAVM_PCCPF_XXX_VSEC_SCTL 0x10c
diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c
index d29bcda121..7137531d49 100644
--- a/src/soc/cavium/cn81xx/twsi.c
+++ b/src/soc/cavium/cn81xx/twsi.c
@@ -20,7 +20,6 @@
#include <soc/clock.h>
#include <device/i2c.h>
#include <device/i2c_simple.h>
-#include <assert.h>
#include <delay.h>
#include <device/mmio.h>
#include <soc/addressmap.h>
diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c
index aaf9085ccf..ae2a91fe0d 100644
--- a/src/soc/cavium/common/ecam.c
+++ b/src/soc/cavium/common/ecam.c
@@ -22,7 +22,6 @@
#include <device/pci.h>
#include <soc/addressmap.h>
#include <soc/ecam.h>
-#include <assert.h>
/**
* Get PCI BAR address from cavium specific extended capability.