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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-08-08 12:46:18 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-08-10 23:24:56 +0000
commit52acef175e42374d463214427678e3e7828960c3 (patch)
treecb844d51ba05d534bffd3c7b54bcd911c774e963 /src/soc/cavium
parenteead87961f909a012a74cbd47effe83c76eaf5e7 (diff)
downloadcoreboot-52acef175e42374d463214427678e3e7828960c3.tar.xz
soc/cavium/cn81xx: Fix minor things
* Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium')
-rw-r--r--src/soc/cavium/cn81xx/Makefile.inc11
-rw-r--r--src/soc/cavium/cn81xx/cbmem.c (renamed from src/soc/cavium/common/cbmem.c)5
-rw-r--r--src/soc/cavium/cn81xx/soc.c3
-rw-r--r--src/soc/cavium/common/Makefile.inc3
4 files changed, 8 insertions, 14 deletions
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index 845ac34961..2179bc7ec8 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -39,16 +39,11 @@ romstage-y += timer.c
romstage-y += spi.c
romstage-y += uart.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
-romstage-< += cpu.c
+romstage-y += cbmem.c
romstage-y += sdram.c
romstage-y += mmu.c
-romstage-y += ../common/cbmem.c
-# BDK coreboot interface
-romstage-y += ../common/bdk-coreboot.c
-
-
################################################################################
# ramstage
@@ -64,12 +59,10 @@ ramstage-y += soc.c
ramstage-y += cpu.c
ramstage-y += cpu_secondary.S
ramstage-y += ecam0.c
+ramstage-y += cbmem.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
-# BDK coreboot interface
-ramstage-y += ../common/bdk-coreboot.c
-
BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0
CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
diff --git a/src/soc/cavium/common/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c
index 401f8b2a65..397fd263d7 100644
--- a/src/soc/cavium/common/cbmem.c
+++ b/src/soc/cavium/cn81xx/cbmem.c
@@ -21,6 +21,7 @@
void *cbmem_top(void)
{
- return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
- MAX_DRAM_ADDRESS);
+ /* Make sure not to overlap with reserved ATF scratchpad */
+ return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB,
+ 4ULL * GiB);
}
diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c
index b575ca4391..8efcb1374c 100644
--- a/src/soc/cavium/cn81xx/soc.c
+++ b/src/soc/cavium/cn81xx/soc.c
@@ -309,7 +309,8 @@ void bootmem_platform_add_ranges(void)
BM_MEM_RESERVED);
/* Scratchpad for ATF SATA quirks */
- bootmem_add_range(sdram_size_mb() * KiB, 1 * MiB, BM_MEM_RESERVED);
+ bootmem_add_range((sdram_size_mb() - 1) * MiB, 1 * MiB,
+ BM_MEM_RESERVED);
}
static void soc_read_resources(device_t dev)
diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc
index 7af8bf58ef..ada8286591 100644
--- a/src/soc/cavium/common/Makefile.inc
+++ b/src/soc/cavium/common/Makefile.inc
@@ -22,13 +22,12 @@ bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c
################################################################################
# romstage
-romstage-y += cbmem.c
romstage-y += bdk-coreboot.c
################################################################################
# ramstage
-ramstage-y += cbmem.c
+ramstage-y += bdk-coreboot.c
CPPFLAGS_common += -Isrc/soc/cavium/common/include