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authorJulius Werner <jwerner@chromium.org>2019-02-20 18:39:22 -0800
committerJulius Werner <jwerner@chromium.org>2019-02-22 06:44:02 +0000
commit7e0dea6317dc74f8aba8c91d0f8e8a7237261c49 (patch)
treec9f476b75f0f9fcfe84aeb00b396723b3bcf7f5b /src/soc/cavium
parent314b5c370b4655bc701985ddf1d1d478067e7baa (diff)
downloadcoreboot-7e0dea6317dc74f8aba8c91d0f8e8a7237261c49.tar.xz
symbols.h: Add macro to define memlayout region symbols
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/cavium')
-rw-r--r--src/soc/cavium/cn81xx/cpu.c2
-rw-r--r--src/soc/cavium/cn81xx/include/soc/cpu.h5
-rw-r--r--src/soc/cavium/cn81xx/mmu.c2
-rw-r--r--src/soc/cavium/common/bootblock.c2
4 files changed, 5 insertions, 6 deletions
diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c
index 9504868dff..b655d8a0ed 100644
--- a/src/soc/cavium/cn81xx/cpu.c
+++ b/src/soc/cavium/cn81xx/cpu.c
@@ -81,7 +81,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id))
return 1;
/* Check stack here, instead of in cpu_secondary.S */
- if ((CONFIG_STACK_SIZE * cpu) > _stack_sec_size)
+ if ((CONFIG_STACK_SIZE * cpu) > REGION_SIZE(stack_sec))
return 1;
/* Write the address of the main entry point */
diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h
index 1c6a30dda9..7d3647bda0 100644
--- a/src/soc/cavium/cn81xx/include/soc/cpu.h
+++ b/src/soc/cavium/cn81xx/include/soc/cpu.h
@@ -18,6 +18,7 @@
#define __SOC_CAVIUM_CN81XX_CPU_H__
#include <stdint.h>
+#include <symbols.h>
/**
* Number of the Core on which the program is currently running.
@@ -70,8 +71,6 @@ void secondary_cpu_init(size_t core_id);
/* Symbols in memlayout.ld */
-extern u8 _stack_sec[];
-extern u8 _estack_sec[];
-#define _stack_sec_size (_estack_sec - _stack_sec)
+DECLARE_REGION(stack_sec)
#endif /* __SOC_CAVIUM_CN81XX_CPU_H__ */
diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c
index d6e7ac5ee1..17b43e77ee 100644
--- a/src/soc/cavium/cn81xx/mmu.c
+++ b/src/soc/cavium/cn81xx/mmu.c
@@ -31,7 +31,7 @@ void soc_mmu_init(void)
* Need to use secure mem attribute, as firmware is running in ARM TZ
* region.
*/
- mmu_config_range((void *)_ttb, _ttb_size, secure_mem);
+ mmu_config_range((void *)_ttb, REGION_SIZE(ttb), secure_mem);
mmu_config_range((void *)_dram, sdram_size_mb() * MiB, secure_mem);
/* IO space has the MSB set and is divided into 4 sub-regions:
* * NCB
diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c
index 7b9d524198..a512dffa00 100644
--- a/src/soc/cavium/common/bootblock.c
+++ b/src/soc/cavium/common/bootblock.c
@@ -42,7 +42,7 @@ void bootblock_main(const uint64_t reg_x0,
base_timestamp = timestamp_get();
/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
- if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
+ if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0)
timestamp_init(base_timestamp);
bootblock_soc_early_init();