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authorPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-11-10 00:35:02 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-03-07 12:47:01 +0000
commitc9b7d1fb57787d7037a5bce031a1300d13f5df40 (patch)
tree57788b70b069229693dae5727cb8acc54eee3c14 /src/soc/cavium
parent7a732b4781e7b83abda3230055d7110e1db730f3 (diff)
downloadcoreboot-c9b7d1fb57787d7037a5bce031a1300d13f5df40.tar.xz
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/cavium')
-rw-r--r--src/soc/cavium/cn81xx/include/soc/memlayout.ld3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index 22226176e7..e4e3490395 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -35,7 +35,8 @@ SECTIONS
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
- VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K)
+ VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K)
+ VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K)
ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
SRAM_END(BOOTROM_OFFSET + 0x80000)