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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-03 09:38:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-09 09:50:40 +0000
commitcb10346cd5a858817e6bd838f424f827c7761d89 (patch)
tree97e618bf27fec0b19bad023d87b7ddaef8e30fd2 /src/soc/cavium
parent909870aba677bf6a30edc2ab971e312cb5826999 (diff)
downloadcoreboot-cb10346cd5a858817e6bd838f424f827c7761d89.tar.xz
soc/cavium: Remove white spaces before tabs
Change-Id: I8213835ac18a31f1c10d80ba07b50d33f8abcbd9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/soc/cavium')
-rw-r--r--src/soc/cavium/cn81xx/gpio.c4
-rw-r--r--src/soc/cavium/cn81xx/include/soc/addressmap.h2
-rw-r--r--src/soc/cavium/cn81xx/spi.c4
-rw-r--r--src/soc/cavium/cn81xx/uart.c6
-rw-r--r--src/soc/cavium/common/bdk-coreboot.c16
5 files changed, 16 insertions, 16 deletions
diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.c
index 84e36d19fd..9de1839094 100644
--- a/src/soc/cavium/cn81xx/gpio.c
+++ b/src/soc/cavium/cn81xx/gpio.c
@@ -37,9 +37,9 @@ union bit_cfg {
u64 filt_cnt : 4; /* Glitch filter counter */
u64 filt_sel : 4; /* Glitch filter select */
u64 tx_od : 1; /* Set Output to Open Drain */
- u64 : 3;
+ u64 : 3;
u64 pin_sel : 10; /* Select type of pin */
- u64 : 38;
+ u64 : 38;
} s;
};
diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h
index f6983064fc..3fb4c9c3e4 100644
--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h
+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h
@@ -36,7 +36,7 @@
/* LMC */
#define LMC0_PF_BAR0 0x87E088000000ULL
-#define LMC0_DDR_PLL_CTL0 0x258
+#define LMC0_DDR_PLL_CTL0 0x258
/* OCLA */
diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c
index 6527f22ea1..2391f4ae76 100644
--- a/src/soc/cavium/cn81xx/spi.c
+++ b/src/soc/cavium/cn81xx/spi.c
@@ -44,7 +44,7 @@ union cavium_spi_cfg {
u64 cslate : 1;
u64 csena : 4; /* Must be one */
u64 clkdiv : 13;
- u64 : 35;
+ u64 : 35;
} s;
};
@@ -69,7 +69,7 @@ union cavium_spi_tx {
u64 leavecs : 1;
u64 : 3;
u64 csid : 2;
- u64 : 42;
+ u64 : 42;
} s;
};
diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c
index 7a9ea3a158..baa9206512 100644
--- a/src/soc/cavium/cn81xx/uart.c
+++ b/src/soc/cavium/cn81xx/uart.c
@@ -34,13 +34,13 @@ union cn81xx_uart_ctl {
u64 uaa_rst : 1;
u64 : 2;
u64 csclk_en : 1;
- u64 : 19;
+ u64 : 19;
u64 h_clkdiv_sel : 3;
- u64 : 1;
+ u64 : 1;
u64 h_clkdiv_rst : 1;
u64 h_clk_byp_sel : 1;
u64 h_clk_en : 1;
- u64 : 33;
+ u64 : 33;
} s;
};
diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c
index ff30edfa79..a6e15e315d 100644
--- a/src/soc/cavium/common/bdk-coreboot.c
+++ b/src/soc/cavium/common/bdk-coreboot.c
@@ -39,10 +39,10 @@
* @param twsi_id which TWSI bus to use
* @param dev_addr Device address (7 bit)
* @param internal_addr
- * Internal address. Can be 0, 1 or 2 bytes in width
+ * Internal address. Can be 0, 1 or 2 bytes in width
* @param num_bytes Number of data bytes to read (1-4)
* @param ia_width_bytes
- * Internal address size in bytes (0, 1, or 2)
+ * Internal address size in bytes (0, 1, or 2)
*
* @return Read data, or -1 on failure
*/
@@ -77,14 +77,14 @@ int64_t bdk_twsix_read_ia(bdk_node_t node, int twsi_id, uint8_t dev_addr,
* @param twsi_id which TWSI interface to use
* @param dev_addr TWSI device address (7 bit only)
* @param internal_addr
- * TWSI internal address (0, 8, or 16 bits)
+ * TWSI internal address (0, 8, or 16 bits)
* @param num_bytes Number of bytes to write (1-8)
* @param ia_width_bytes
- * internal address width, in bytes (0, 1, 2)
- * @param data Data to write. Data is written MSB first on the twsi bus, and
- * only the lower num_bytes bytes of the argument are valid. (If
- * a 2 byte write is done, only the low 2 bytes of the argument is
- * used.
+ * internal address width, in bytes (0, 1, 2)
+ * @param data Data to write. Data is written MSB first on the twsi bus,
+ * and only the lower num_bytes bytes of the argument are
+ * valid. If a 2 byte write is done, only the low 2 bytes of
+ * the argument is used.
*
* @return Zero on success, -1 on error
*/