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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-29 18:31:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:27:53 +0200 |
| commit | 038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch) | |
| tree | 8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/dmp | |
| parent | f9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff) | |
| download | coreboot-038e7247dc9705ff2d47dd90ec9a807f6feb52ba.tar.xz | |
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/dmp')
| -rw-r--r-- | src/soc/dmp/vortex86ex/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/dmp/vortex86ex/northbridge.c b/src/soc/dmp/vortex86ex/northbridge.c index 62c68e062e..e60481c785 100644 --- a/src/soc/dmp/vortex86ex/northbridge.c +++ b/src/soc/dmp/vortex86ex/northbridge.c @@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev) ss = pci_read_config16(mc_dev, 0x6c); ss = ((ss >> 8) & 0xf); tomk = (2 * 1024) << ss; - printk(BIOS_DEBUG, "I would set ram size to %ld Mbytes\n", (tomk >> 10)); + printk(BIOS_DEBUG, "I would set RAM size to %ld Mbytes\n", (tomk >> 10)); /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) |