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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-20 20:30:02 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-22 12:18:41 +0000 |
commit | a9506dbaf410d9b2d297661f51f0e0b9842170e1 (patch) | |
tree | b442dc8f162549abb0e11377c80bc624a69e896a /src/soc/imgtec/pistachio/ddr2_init.c | |
parent | 9c8044bdcd2aa77d8a8092b270ca36fd3aa23b87 (diff) | |
download | coreboot-a9506dbaf410d9b2d297661f51f0e0b9842170e1.tar.xz |
arch/mips: Fix <arch/mmio.h> prototypes
These signatures need to be consistent across different
architectures.
Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/imgtec/pistachio/ddr2_init.c')
-rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 128 |
1 files changed, 64 insertions, 64 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index e05fda5b5c..39b553df24 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -33,31 +33,31 @@ int init_ddr2(void) * writes have already happened to DDR - note must be done together, * not sequentially */ - write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000); - write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); + write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000); + write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); /* * Dummy read to fence the access between the reset above * and thw DDR controller writes below */ - read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); + read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); /* Timings for 400MHz * therefore 200MHz (5ns) uMCTL (Internal) Rate */ /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); + write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); + write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000); + write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000); /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); + write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); /* DTUAWDT DTU Address Width Register * 1:0 column_addr_width Def 10 - 7 3 10 bits * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) * 7:6 row_addr_width Def 14 - 13 1 3 bits * 10:9 number_ranks Def 1 - 1 0 0 1 Rank */ - write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); + write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); /* MCFG * 0 BL 0 = 4 1 = 8 * 1 RDRIMM 0 @@ -75,7 +75,7 @@ int init_ddr2(void) * 23:22 mDDR/LPDDR2 Enable 0 * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 */ - write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, + write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060000 | (BL8 ? 0x1 : 0x0)); /* MCFG1: Memory Configuration-1 Register * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB @@ -85,7 +85,7 @@ int init_ddr2(void) * 30:24 Reserved * 31 c_active_in_pin exit auto clk stop NA 0 */ - write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); + write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); /* DCR DRAM Config * 2:0 SDRAM => DDR2 2 * 3 DDR 8 Bank 1 @@ -99,7 +99,7 @@ int init_ddr2(void) * 30 RDIMM NA 0 * 31 TPD LPDDR2 0 */ - write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A); + write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A); /* Generate to use with PHY and PCTL * MR0 : MR Register, bits 12:0 imported dfrom MR * 2:0 BL 8 011 @@ -112,7 +112,7 @@ int init_ddr2(void) * 15:13 RSVD RSVD * 31:16 Reserved */ - write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); + write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); /* MR1 : EMR Register * Generate to use with PHY and PCTL * 0 DE DLL Enable 0 Disable 1 @@ -126,7 +126,7 @@ int init_ddr2(void) * 15:13 RSVD * 31:16 Reserved */ - write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); + write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); /* MR2 : EMR2 Register * Generate to use with PHY and PCTL * 2:0 PASR, NA 000 @@ -136,7 +136,7 @@ int init_ddr2(void) * 15:8 RSVD * 31:16 Reserved */ - write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000); + write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000); /* DSGCR * 0 PUREN Def 1 * 1 BDISEN Def 1 @@ -159,9 +159,9 @@ int init_ddr2(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); + write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); + write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 2 * 4:2 tRTP 3 @@ -173,7 +173,7 @@ int init_ddr2(void) * 30:25 tRC 24 (23) * 31 tCCD 0 BL/2 Cas to Cas */ - write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E); + write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E); /* DTPR1 : DRAM Timing Params 1 * 1:0 ODT On/Off Del Std 0 * 2 tRTW Rd2Wr Del 0 std 1 +1 0 @@ -186,7 +186,7 @@ int init_ddr2(void) * 29:27 tDQSCKmax 1 * 31:30 Reserved */ - write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092); + write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092); /* DTPR2 : DRAM Timing Params 2 * 9:0 tXS exit SR def 200, 200d * 14:10 tXP PD Exit Del 8 3 @@ -194,19 +194,19 @@ int init_ddr2(void) * 28:19 tDLLK DLL Lock time 200d * 32:29 Reserved */ - write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8); + write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8); /* PTR0 : PHY Timing Params 0 * 5:0 tDLLRST Def 27 * 17:6 tDLLLOCK Def 2750 * 21:18 tITMSRST Def 8 * 31:22 Reserved 0 */ - write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); + write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); /* PTR1 : PHY Timing Params 1 * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880 * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0 */ - write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880); + write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880); /* DQS gating configuration: passive windowing mode */ /* * PGCR: PHY General cofiguration register @@ -228,25 +228,25 @@ int init_ddr2(void) * 30 loopback DQS gating 0 * 31 loopback mode 0 */ - write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); + write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) return DDR_TIMEOUT; /* PIR : use PHY for DRAM Init */ - write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF); + write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF); /* PGSR : Wait for DRAM Init Done */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) return DDR_TIMEOUT; /* Disable Impedance Calibration */ - write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); + write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); + write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, 0x00000001)) return DDR_TIMEOUT; /* POWCTL : Start the memory Power Up seq*/ - write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001); + write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001); /* POWSTAT : wait for POWER_UP_DONE */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, 0x00000001)) @@ -259,84 +259,84 @@ int init_ddr2(void) * 30:19 Reserved 0 * 31 Update 1 */ - write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); + write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); /* TMRD : t_mrd Timing Register -- Range 2 to 3 */ - write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002); + write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002); /* * TRFC : t_rfc Timing Register -- Range 15 to 131 * 195ns / 2.5ns 78 x4E */ - write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); + write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); /* TRP : t_rp Timing Register -- Range 3 to 7 * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 * 17:16 rpea_extra tRPall 8 bank 1 */ - write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006); + write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006); /* TAL : Additive Latency Register -- AL in MR1 */ - write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); + write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); + write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); + write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); + write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); /* TCWL : CAS Write Latency Register --CASL-1 */ - write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); + write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); /* * TRAS : Activate to Precharge cmd time * Range 8 to 24: 45ns / 2.5ns = 18d */ - write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); + write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); /* * TRC : Min. ROW cycle time * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 */ - write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); + write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); /* * TRCD : Row to Column Delay * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6 */ - write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); + write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); /* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/ - write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); + write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); /* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */ - write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003); /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 */ - write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); + write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); /* * TWTR : Write to read turn around time * Range 2 to 4: 7.3ns / 2.5ns = 3 */ - write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003); /* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/ - write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8); + write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8); /* * TXP : Exit Power Down to first valid cmd * tXP 2, Settingto 3 to match PHY */ - write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); /* * TDQS : t_dqs Timing Register * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 */ - write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); + write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); /*TRTW : Read to Write turn around time Def 3 * Actual gap t_bl + t_rtw */ - write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); /* TCKE : CKE min pulse width DEf 3 */ - write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); /* * TXPDLL : Slow Exit Power Down to first valid cmd delay * tXARDS 10+AL = 10 */ - write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); + write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); /* * TCKESR : Min CKE Low width for Self refresh entry to exit * t_ckesr = 0 DDR2 */ - write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000); + write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000); /* SCFG : State Configuration Register (Enabling Self Refresh) * 0 LP_en Leave Off for Bring Up 0 * 5:1 Reserved @@ -346,17 +346,17 @@ int init_ddr2(void) * 16:12 Additional delay on accertion of ac_pdd 4 * 31:17 Reserved */ - write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); + write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); /* * DFITPHYWRDATA : dfi_wrdata_en to drive wr data * DFI Clks wrdata_en to wrdata Def 1 */ - write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); + write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); /* * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid * DFI clks max rddata_en to rddata_valid Def 15 */ - write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); + write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 * 3:0 cmd_opcode PREA 00001 * 16:4 cmd_addr 0 @@ -365,12 +365,12 @@ int init_ddr2(void) * 27:24 cmddelay 0 * 30:24 Reserved */ - write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001); + write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001); /* MRS cmd wait for completion */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001)) return DDR_TIMEOUT; /* SCTL : UPCTL switch INIT CONFIG State */ - write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); + write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); /* STAT : Wait for Switch INIT to Config State */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) return DDR_TIMEOUT; @@ -379,17 +379,17 @@ int init_ddr2(void) * 1 dfi_freq_ratio_en 1 * 2 dfi_data_byte_disable_en 1 */ - write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003); /* DFISTCFG1 : Enable various DFI support * 0 dfi_dram_clk_disable_en 1 * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 */ - write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); + write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); /* DFISTCFG2 : Enable Parity and asoc interrupt * 0 dfi_parity_in Enable 1 * 1 Interrupt on dfi_parity_error 1 */ - write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); + write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); /* DFILPCFG0 : DFI Low Power Interface Configuration * 0 Enable DFI LP IF during PD 1 * 3:1 Reserved @@ -403,7 +403,7 @@ int init_ddr2(void) * 27:25 Reserved * 31:28 DFI LP Deep Power Down Value 0 */ - write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); + write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); /* DFIODTCFG : DFI ODT Configuration * Only Enabled on Rank0 Writes * 0 rank0_odt_read_nsel 0 @@ -411,14 +411,14 @@ int init_ddr2(void) * 2 rank0_odt_write_nsel 0 * 3 rank0_odt_write_sel 1 */ - write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); + write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); /* DFIODTCFG1 : DFI ODT Configuration * 4:0 odt_lat_w 4 * 12:8 odt_lat_r 0 Def * 4:0 odt_len_bl8_w 6 Def * 12:8 odt_len_bl8_r 6 Def */ - write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004); + write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004); /* DCFG : DRAM Density 256 Mb 16 Bit IO Width * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 * 5:2 Density 2Gb = 5 @@ -427,14 +427,14 @@ int init_ddr2(void) * 10:8 Address Map R/B/C = 1 * 31:11 Reserved */ - write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); + write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); /* PCFG_0 : Port 0 AXI config */ if (BL8) - write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); + write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); else - write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0); + write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0); /* SCTL : UPCTL switch Config to ACCESS State */ - write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); + write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); /* STAT : Wait for switch CFG -> GO State */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) return DDR_TIMEOUT; |