diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-05-21 13:29:45 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-21 02:05:17 +0100 |
| commit | 6b95406ff3d44679d2e0139236c134655b12b927 (patch) | |
| tree | 03248c5604b395f791beaeaf3de050ffb4653ac9 /src/soc/imgtec/pistachio/include | |
| parent | f6d3bd4815d2d442eb3cdf418ba3074134e5bd7d (diff) | |
| download | coreboot-6b95406ff3d44679d2e0139236c134655b12b927.tar.xz | |
imgtec/pistachio: DDR2, DDR3: DQS gate early
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/imgtec/pistachio/include')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h index a0f661b8fd..a9d18a0f3b 100644 --- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h +++ b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h @@ -103,6 +103,7 @@ #define DDRPHY_DLLGCR_OFFSET (0x0010) #define DDRPHY_PTR0_OFFSET (0x0018) #define DDRPHY_PTR1_OFFSET (0x001C) +#define DDRPHY_DXCCR_OFFSET (0x0028) #define DDRPHY_DSGCR_OFFSET (0x002C) #define DDRPHY_DCR_OFFSET (0x0030) #define DDRPHY_DTPR0_OFFSET (0x0034) @@ -120,6 +121,8 @@ #define DDRPHY_BISTAR2_OFFSET (0x011C) #define DDRPHY_BISTUDPR_OFFSET (0x0120) #define DDRPHY_BISTGSR_OFFSET (0x0124) +#define DDRPHY_ZQ0CR0_OFFSET (0x0180) +#define DDRPHY_ZQ1CR0_OFFSET (0x0190) #define DDR_TIMEOUT_VALUE_US 100000 |